c7c90f47b0
This fixes SPI with PSRAM allocated buffers. DMA with SPI2 was attempted but produced junk output. This manual copy is less than 2x slower than DMA when not interrupted. Fixes #3339
376 lines
13 KiB
C
376 lines
13 KiB
C
/*
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* This file is part of the MicroPython project, http://micropython.org/
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2016 Scott Shawcroft
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "shared-bindings/busio/SPI.h"
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#include "py/mperrno.h"
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#include "py/runtime.h"
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#include "boards/board.h"
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#include "shared-bindings/microcontroller/Pin.h"
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#include "supervisor/shared/rgb_led_status.h"
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static bool spi_never_reset[SOC_SPI_PERIPH_NUM];
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// Store one lock handle per device so that we can free it.
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static spi_bus_lock_dev_handle_t lock_dev_handle[SOC_SPI_PERIPH_NUM];
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static intr_handle_t intr_handle[SOC_SPI_PERIPH_NUM];
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void spi_reset(void) {
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for (spi_host_device_t host_id = SPI2_HOST; host_id < SOC_SPI_PERIPH_NUM; host_id++) {
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if (spi_never_reset[host_id]) {
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continue;
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}
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bool in_use = false;
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if (lock_dev_handle[host_id] != NULL) {
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spi_bus_lock_unregister_dev(lock_dev_handle[host_id]);
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lock_dev_handle[host_id] = NULL;
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in_use = true;
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}
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if (intr_handle[host_id] != NULL) {
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esp_intr_free(intr_handle[host_id]);
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intr_handle[host_id] = NULL;
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in_use = true;
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}
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if (in_use) {
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spi_bus_free(host_id);
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}
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}
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}
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// This is copied in from the ESP-IDF because it is static.
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// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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static bool bus_uses_iomux_pins(spi_host_device_t host, const spi_bus_config_t* bus_config)
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{
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if (bus_config->sclk_io_num>=0 &&
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bus_config->sclk_io_num != spi_periph_signal[host].spiclk_iomux_pin) return false;
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if (bus_config->quadwp_io_num>=0 &&
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bus_config->quadwp_io_num != spi_periph_signal[host].spiwp_iomux_pin) return false;
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if (bus_config->quadhd_io_num>=0 &&
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bus_config->quadhd_io_num != spi_periph_signal[host].spihd_iomux_pin) return false;
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if (bus_config->mosi_io_num >= 0 &&
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bus_config->mosi_io_num != spi_periph_signal[host].spid_iomux_pin) return false;
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if (bus_config->miso_io_num>=0 &&
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bus_config->miso_io_num != spi_periph_signal[host].spiq_iomux_pin) return false;
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return true;
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}
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// End copied code.
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static bool spi_bus_is_free(spi_host_device_t host_id) {
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return spi_bus_get_attr(host_id) == NULL;
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}
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static void spi_interrupt_handler(void *arg) {
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// busio_spi_obj_t *self = arg;
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}
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// The interrupt may get invoked by the bus lock.
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static void spi_bus_intr_enable(void *self)
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{
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esp_intr_enable(((busio_spi_obj_t *)self)->interrupt);
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}
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// The interrupt is always disabled by the ISR itself, not exposed
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static void spi_bus_intr_disable(void *self)
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{
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esp_intr_disable(((busio_spi_obj_t *)self)->interrupt);
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}
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void common_hal_busio_spi_construct(busio_spi_obj_t *self,
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const mcu_pin_obj_t * clock, const mcu_pin_obj_t * mosi,
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const mcu_pin_obj_t * miso) {
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spi_bus_config_t bus_config;
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bus_config.mosi_io_num = mosi != NULL ? mosi->number : -1;
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bus_config.miso_io_num = miso != NULL ? miso->number : -1;
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bus_config.sclk_io_num = clock != NULL ? clock->number : -1;
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bus_config.quadwp_io_num = -1;
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bus_config.quadhd_io_num = -1;
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bus_config.max_transfer_sz = 0; // Uses the default
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bus_config.flags = SPICOMMON_BUSFLAG_MASTER | SPICOMMON_BUSFLAG_SCLK |
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(mosi != NULL ? SPICOMMON_BUSFLAG_MOSI : 0) |
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(miso != NULL ? SPICOMMON_BUSFLAG_MISO : 0);
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bus_config.intr_flags = 0;
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// RAM and Flash is often on SPI1 and is unsupported by the IDF so use it as
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// a flag value.
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spi_host_device_t host_id = SPI1_HOST;
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self->connected_through_gpio = true;
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// Try and save SPI2 for pins that are on the IOMUX
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if (bus_uses_iomux_pins(SPI2_HOST, &bus_config) && spi_bus_is_free(SPI2_HOST)) {
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host_id = SPI2_HOST;
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self->connected_through_gpio = false;
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} else if (spi_bus_is_free(SPI3_HOST)) {
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host_id = SPI3_HOST;
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} else if (spi_bus_is_free(SPI2_HOST)) {
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host_id = SPI2_HOST;
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}
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if (host_id == SPI1_HOST) {
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mp_raise_ValueError(translate("All SPI peripherals are in use"));
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}
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esp_err_t result = spi_bus_initialize(host_id, &bus_config, host_id /* dma channel */);
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if (result == ESP_ERR_NO_MEM) {
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mp_raise_msg(&mp_type_MemoryError, translate("ESP-IDF memory allocation failed"));
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} else if (result == ESP_ERR_INVALID_ARG) {
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mp_raise_ValueError(translate("Invalid pins"));
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}
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// After this point, we need to deinit to free IDF memory so fill out self's pins.
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self->clock_pin = clock;
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self->MOSI_pin = mosi;
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self->MISO_pin = miso;
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self->host_id = host_id;
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spi_bus_lock_dev_config_t config = { .flags = 0 };
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// The returned lock is stored in the bus lock but must be freed separately with
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// spi_bus_lock_unregister_dev.
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result = spi_bus_lock_register_dev(spi_bus_get_attr(host_id)->lock,
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&config,
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&self->lock);
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if (result == ESP_ERR_NO_MEM) {
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common_hal_busio_spi_deinit(self);
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mp_raise_msg(&mp_type_MemoryError, translate("ESP-IDF memory allocation failed"));
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}
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lock_dev_handle[host_id] = self->lock;
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result = esp_intr_alloc(spicommon_irqsource_for_host(host_id),
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bus_config.intr_flags | ESP_INTR_FLAG_INTRDISABLED,
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spi_interrupt_handler, self, &self->interrupt);
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if (result == ESP_ERR_NO_MEM) {
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common_hal_busio_spi_deinit(self);
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mp_raise_msg(&mp_type_MemoryError, translate("ESP-IDF memory allocation failed"));
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}
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intr_handle[host_id] = self->interrupt;
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spi_bus_lock_set_bg_control(spi_bus_get_attr(host_id)->lock, spi_bus_intr_enable, spi_bus_intr_disable, self);
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spi_hal_context_t* hal = &self->hal_context;
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// spi_hal_init clears the given hal context so set everything after.
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spi_hal_init(hal, host_id);
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// We don't use native CS.
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// hal->cs_setup = 0;
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// hal->cs_hold = 0;
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// hal->cs_pin_id = 0;
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hal->sio = 0;
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hal->half_duplex = 0;
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// hal->tx_lsbfirst = 0;
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// hal->rx_lsbfirst = 0;
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hal->no_compensate = 1;
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// Ignore CS bits
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// We don't use cmd, addr or dummy bits.
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// hal->cmd = 0;
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// hal->cmd_bits = 0;
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// hal->addr_bits = 0;
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// hal->dummy_bits = 0;
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// hal->addr = 0;
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hal->io_mode = SPI_LL_IO_MODE_NORMAL;
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common_hal_busio_spi_configure(self, 250000, 0, 0, 8);
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}
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void common_hal_busio_spi_never_reset(busio_spi_obj_t *self) {
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spi_never_reset[self->host_id] = true;
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common_hal_never_reset_pin(self->clock_pin);
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common_hal_never_reset_pin(self->MOSI_pin);
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common_hal_never_reset_pin(self->MISO_pin);
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}
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bool common_hal_busio_spi_deinited(busio_spi_obj_t *self) {
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return self->clock_pin == NULL;
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}
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void common_hal_busio_spi_deinit(busio_spi_obj_t *self) {
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if (common_hal_busio_spi_deinited(self)) {
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return;
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}
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spi_never_reset[self->host_id] = false;
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if (self->lock != NULL) {
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spi_bus_lock_unregister_dev(self->lock);
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lock_dev_handle[self->host_id] = NULL;
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}
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if (self->interrupt != NULL) {
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esp_intr_free(self->interrupt);
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intr_handle[self->host_id] = NULL;
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}
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spi_bus_free(self->host_id);
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common_hal_reset_pin(self->clock_pin);
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common_hal_reset_pin(self->MOSI_pin);
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common_hal_reset_pin(self->MISO_pin);
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self->clock_pin = NULL;
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}
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bool common_hal_busio_spi_configure(busio_spi_obj_t *self,
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uint32_t baudrate, uint8_t polarity, uint8_t phase, uint8_t bits) {
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if (baudrate == self->target_frequency &&
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polarity == self->polarity &&
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phase == self->phase &&
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bits == self->bits) {
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return true;
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}
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self->hal_context.mode = polarity << 1 | phase;
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self->polarity = polarity;
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self->phase = phase;
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self->bits = bits;
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self->target_frequency = baudrate;
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self->hal_context.timing_conf = &self->timing_conf;
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esp_err_t result = spi_hal_get_clock_conf(&self->hal_context,
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self->target_frequency,
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128 /* duty_cycle */,
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self->connected_through_gpio,
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0 /* input_delay_ns */,
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&self->real_frequency,
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&self->timing_conf);
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if (result != ESP_OK) {
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return false;
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}
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spi_hal_setup_device(&self->hal_context);
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return true;
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}
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bool common_hal_busio_spi_try_lock(busio_spi_obj_t *self) {
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// If our lock has already been taken then return false because someone else
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// may already grabbed it in our call stack.
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if (self->has_lock) {
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return false;
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}
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// Wait to grab the lock from another task.
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esp_err_t result = spi_bus_lock_acquire_start(self->lock, portMAX_DELAY);
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self->has_lock = result == ESP_OK;
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return self->has_lock;
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}
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bool common_hal_busio_spi_has_lock(busio_spi_obj_t *self) {
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return self->has_lock;
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}
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void common_hal_busio_spi_unlock(busio_spi_obj_t *self) {
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spi_bus_lock_acquire_end(self->lock);
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self->has_lock = false;
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}
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bool common_hal_busio_spi_write(busio_spi_obj_t *self,
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const uint8_t *data, size_t len) {
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return common_hal_busio_spi_transfer(self, data, NULL, len);
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}
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bool common_hal_busio_spi_read(busio_spi_obj_t *self,
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uint8_t *data, size_t len, uint8_t write_value) {
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return common_hal_busio_spi_transfer(self, NULL, data, len);
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}
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bool common_hal_busio_spi_transfer(busio_spi_obj_t *self, const uint8_t *data_out, uint8_t *data_in, size_t len) {
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if (len == 0) {
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return true;
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}
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spi_hal_context_t* hal = &self->hal_context;
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hal->send_buffer = NULL;
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hal->rcv_buffer = NULL;
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// Reset timing_conf in case we've moved since the last time we used it.
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hal->timing_conf = &self->timing_conf;
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lldesc_t tx_dma __attribute__((aligned(16)));
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lldesc_t rx_dma __attribute__((aligned(16)));
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hal->dmadesc_tx = &tx_dma;
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hal->dmadesc_rx = &rx_dma;
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hal->dmadesc_n = 1;
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size_t burst_length;
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// If both of the incoming pointers are DMA capable then use DMA. Otherwise, do
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// bursts the size of the SPI data buffer without DMA.
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if ((data_out == NULL || esp_ptr_dma_capable(data_out)) &&
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(data_in == NULL || esp_ptr_dma_capable(data_out))) {
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hal->dma_enabled = 1;
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burst_length = LLDESC_MAX_NUM_PER_DESC;
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} else {
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hal->dma_enabled = 0;
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burst_length = sizeof(hal->hw->data_buf);
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}
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// This rounds up.
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size_t burst_count = (len + burst_length - 1) / burst_length;
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for (size_t i = 0; i < burst_count; i++) {
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size_t offset = burst_length * i;
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size_t this_length = len - offset;
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if (this_length > burst_length) {
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this_length = burst_length;
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}
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hal->tx_bitlen = this_length * self->bits;
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hal->rx_bitlen = this_length * self->bits;
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if (data_out != NULL) {
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hal->send_buffer = (uint8_t*) data_out + offset;
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}
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if (data_in != NULL) {
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hal->rcv_buffer = data_in + offset;
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}
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spi_hal_setup_trans(hal);
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spi_hal_prepare_data(hal);
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spi_hal_user_start(hal);
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// TODO: Switch to waiting on a lock that is given by an interrupt.
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while (!spi_hal_usr_is_done(hal)) {
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RUN_BACKGROUND_TASKS;
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}
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spi_hal_fetch_result(hal);
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}
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hal->dmadesc_tx = NULL;
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hal->dmadesc_rx = NULL;
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hal->dmadesc_n = 0;
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return true;
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}
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uint32_t common_hal_busio_spi_get_frequency(busio_spi_obj_t* self) {
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return self->real_frequency;
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}
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uint8_t common_hal_busio_spi_get_phase(busio_spi_obj_t* self) {
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return self->phase;
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}
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uint8_t common_hal_busio_spi_get_polarity(busio_spi_obj_t* self) {
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return self->polarity;
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}
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