8da39fd182
The Cortex-M7 CPU will do speculative loads from any memory location that is not explicitly forbidden. This includes the QSPI memory-mapped region starting at 0x90000000 and with size 256MiB. Speculative loads to this QSPI region may 1) interfere with the QSPI peripheral registers (eg the address register) if the QSPI is not in memory-mapped mode; 2) attempt to access data outside the configured size of the QSPI flash when it is in memory-mapped mode. Both of these scenarios will lead to issues with the QSPI peripheral (eg Cortex bus lock up in scenario 2). To prevent such speculative loads from interfering with the peripheral the MPU is configured in this commit to restrict access to the QSPI mapped region: when not memory mapped the entire region is forbidden; when memory mapped only accesses to the valid flash size are permitted. |
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| bare-arm | ||
| cc3200 | ||
| esp32 | ||
| esp8266 | ||
| javascript | ||
| minimal | ||
| nrf | ||
| pic16bit | ||
| qemu-arm | ||
| samd | ||
| stm32 | ||
| teensy | ||
| unix | ||
| windows | ||
| zephyr | ||