4e25a4f6b3
Doing a squash merge to avoid having the `slc_cli_linux` .zip files in the history. They were added in one commit and removed and replaced with a submodule in another. * Initial commit for xg24 * Fix SLC issue * Fix SLC extract fail * Change board's name * Correct spelling of code Build immediately after slc generate * Remove VID and PID * Change creator and creation id * Apply new creator_id and creation_id * Update makefile, error message, mcu_processor function * Update mpconfigboard.mk * Update Board extensions, PORT_DEPS * Update makefile * Add exclude_patterns * Show java, jinja2 version * Show path for debugging CI * Add requirements-dev for slc * Add PATH slc_cli * Update background function * Add jinja2 PATH * Show PATH * Update jinja2 path * Update jinja2 path * Update jinja2 path * Update jinja2 path * Change slc folder * Change markupsafe folder * Add symbolic link for slc * Update makefile * Update makefile * Update MX25R3235F.toml from submodule nvm.toml * alphabetize the list * Remove slc_cli_linux folder * Update slc_cli submodule --------- Co-authored-by: Chat Nguyen <cvnguyen@silabs.com> Co-authored-by: silabs-ChatNguyen <chat.nguyen@silabs.com> Co-authored-by: silabs-ChatNguyen <126220343+silabs-ChatNguyen@users.noreply.github.com>
134 lines
4.3 KiB
C
134 lines
4.3 KiB
C
/*
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* This file is part of Adafruit for EFR32 project
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*
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* The MIT License (MIT)
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*
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* Copyright 2023 Silicon Laboratories Inc. www.silabs.com
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "py/runtime.h"
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#include "common-hal/watchdog/WatchDogTimer.h"
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#include "shared-bindings/watchdog/__init__.h"
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#include "shared-bindings/microcontroller/__init__.h"
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#include "em_wdog.h"
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#include "em_cmu.h"
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void common_hal_watchdog_feed(watchdog_watchdogtimer_obj_t *self) {
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WDOGn_Feed(DEFAULT_WDOG);
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}
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void common_hal_watchdog_deinit(watchdog_watchdogtimer_obj_t *self) {
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WDOG_Enable(false);
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}
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void watchdog_reset(void) {
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common_hal_watchdog_deinit(&common_hal_mcu_watchdogtimer_obj);
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}
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mp_float_t common_hal_watchdog_get_timeout(watchdog_watchdogtimer_obj_t *self) {
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return self->timeout;
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}
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void common_hal_watchdog_set_timeout(watchdog_watchdogtimer_obj_t *self,
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mp_float_t new_timeout) {
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// Max timeout is 256000 ms
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uint64_t timeout = new_timeout * 1000;
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mp_arg_validate_int_max(timeout, 256000, MP_QSTR_WatchDogTimeout);
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if ((uint32_t)self->timeout != (uint32_t)new_timeout) {
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// Watchdog Initialize settings
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WDOG_Init_TypeDef wdogInit = WDOG_INIT_DEFAULT;
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switch ((uint32_t)new_timeout)
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{
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case 1:
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wdogInit.perSel = wdogPeriod_1k;
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break;
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case 2:
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wdogInit.perSel = wdogPeriod_2k;
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break;
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case 4:
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wdogInit.perSel = wdogPeriod_4k;
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break;
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case 8:
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wdogInit.perSel = wdogPeriod_8k;
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break;
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case 16:
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wdogInit.perSel = wdogPeriod_16k;
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break;
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case 32:
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wdogInit.perSel = wdogPeriod_32k;
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break;
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case 64:
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wdogInit.perSel = wdogPeriod_64k;
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break;
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case 128:
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wdogInit.perSel = wdogPeriod_128k;
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break;
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case 256:
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wdogInit.perSel = wdogPeriod_256k;
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break;
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default:
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mp_raise_ValueError(
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translate("Timeout value supported: 1,2,4,8,16,32,64,128,256"));
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}
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self->timeout = new_timeout;
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// Enable clock for the WDOG module; has no effect on xG21
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CMU_ClockEnable(cmuClock_WDOG0, true);
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// ULFRCO as clock source
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CMU_ClockSelectSet(cmuClock_WDOG0, cmuSelect_ULFRCO);
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wdogInit.em1Run = true;
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wdogInit.em2Run = true;
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wdogInit.em3Run = true;
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// Initializing watchdog with chosen settings
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WDOGn_Init(DEFAULT_WDOG, &wdogInit);
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}
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}
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watchdog_watchdogmode_t common_hal_watchdog_get_mode
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(watchdog_watchdogtimer_obj_t *self) {
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return self->mode;
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}
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void common_hal_watchdog_set_mode(watchdog_watchdogtimer_obj_t *self,
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watchdog_watchdogmode_t new_mode) {
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if (self->mode != new_mode) {
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if (new_mode == WATCHDOGMODE_RAISE) {
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mp_raise_NotImplementedError(
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translate("RAISE mode is not implemented"));
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} else if (new_mode == WATCHDOGMODE_NONE) {
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self->mode = WATCHDOGMODE_NONE;
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common_hal_watchdog_deinit(self);
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}
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self->mode = new_mode;
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common_hal_watchdog_set_timeout(self, self->timeout);
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}
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}
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