cf9fc7346d
To use HSE bypass mode the board should define:
#define MICROPY_HW_CLK_USE_BYPASS (1)
If this is not defined, or is defined to 0, then HSE oscillator mode is
used.
615 lines
21 KiB
C
615 lines
21 KiB
C
/*
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* This file is part of the MicroPython project, http://micropython.org/
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*
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* Taken from ST Cube library and modified. See below for original header.
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2013, 2014 Damien P. George
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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/**
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******************************************************************************
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* @file system_stm32.c
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* @author MCD Application Team
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* @version V1.0.1
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* @date 26-February-2014
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* @brief CMSIS Cortex-M4/M7 Device Peripheral Access Layer System Source File.
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*
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* This file provides two functions and one global variable to be called from
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* user application:
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* - SystemInit(): This function is called at startup just after reset and
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* before branch to main program. This call is made inside
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* the "startup_stm32.s" file.
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*
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* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
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* by the user application to setup the SysTick
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* timer or configure other parameters.
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*
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*
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of STMicroelectronics nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************
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*/
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/** @addtogroup CMSIS
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* @{
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*/
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/** @addtogroup stm32fxxx_system
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* @{
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*/
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/** @addtogroup STM32Fxxx_System_Private_Includes
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* @{
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*/
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#include "py/mphal.h"
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void __fatal_error(const char *msg);
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/**
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* @}
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*/
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/** @addtogroup STM32Fxxx_System_Private_TypesDefinitions
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* @{
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*/
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/**
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* @}
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*/
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/** @addtogroup STM32Fxxx_System_Private_Defines
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* @{
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*/
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#if defined(STM32F4) || defined(STM32F7)
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#define CONFIG_RCC_CR_1ST (RCC_CR_HSION)
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#define CONFIG_RCC_CR_2ND (RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON)
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#define CONFIG_RCC_PLLCFGR (0x24003010)
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#if defined(STM32F4)
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const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
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const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
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#elif defined(STM32F7)
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const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
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const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
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#endif
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#elif defined(STM32L4)
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#define CONFIG_RCC_CR_1ST (RCC_CR_MSION)
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#define CONFIG_RCC_CR_2ND (RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_HSION | RCC_CR_PLLON)
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#define CONFIG_RCC_PLLCFGR (0x00001000)
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/*
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* FIXME Do not know why I have to define these arrays here! they should be defined in the
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* hal_rcc-file!!
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*
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*/
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const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
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const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
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const uint32_t MSIRangeTable[12] = {100000, 200000, 400000, 800000, 1000000, 2000000, \
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4000000, 8000000, 16000000, 24000000, 32000000, 48000000};
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#elif defined(STM32H7)
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#define CONFIG_RCC_CR_1ST (RCC_CR_HSION)
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#define CONFIG_RCC_CR_2ND (~0xEAF6ED7F)
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#define CONFIG_RCC_PLLCFGR (0x00000000)
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#define SRAM_BASE D1_AXISRAM_BASE
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#define FLASH_BASE FLASH_BANK1_BASE
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uint32_t SystemD2Clock = 64000000;
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const uint8_t D1CorePrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
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#else
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#error Unknown processor
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#endif
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/************************* Miscellaneous Configuration ************************/
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/*!< Uncomment the following line if you need to relocate your vector Table in
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Internal SRAM. */
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/* #define VECT_TAB_SRAM */
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#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
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This value must be a multiple of 0x200. */
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/******************************************************************************/
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/**
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* @}
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*/
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/** @addtogroup STM32Fxxx_System_Private_Macros
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* @{
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*/
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/**
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* @}
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*/
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/** @addtogroup STM32Fxxx_System_Private_Variables
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* @{
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*/
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/* This variable is updated in three ways:
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1) by calling CMSIS function SystemCoreClockUpdate()
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2) by calling HAL API function HAL_RCC_GetHCLKFreq()
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3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
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Note: If you use this function to configure the system clock; then there
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is no need to call the 2 first functions listed above, since SystemCoreClock
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variable is updated automatically.
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*/
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uint32_t SystemCoreClock = 16000000;
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/**
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* @}
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*/
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/** @addtogroup STM32Fxxx_System_Private_FunctionPrototypes
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* @{
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*/
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/**
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* @}
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*/
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/** @addtogroup STM32Fxxx_System_Private_Functions
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* @{
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*/
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/**
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* @brief Setup the microcontroller system
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* Initialize the FPU setting, vector table location and External memory
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* configuration.
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* @param None
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* @retval None
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*/
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void SystemInit(void)
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{
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/* FPU settings ------------------------------------------------------------*/
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#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
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SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
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#endif
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/* Reset the RCC clock configuration to the default reset state ------------*/
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/* Set HSION bit */
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RCC->CR |= CONFIG_RCC_CR_1ST;
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/* Reset CFGR register */
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RCC->CFGR = 0x00000000;
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/* Reset HSEON, CSSON and PLLON bits */
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RCC->CR &= ~ CONFIG_RCC_CR_2ND;
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/* Reset PLLCFGR register */
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RCC->PLLCFGR = CONFIG_RCC_PLLCFGR;
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#if defined(STM32H7)
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/* Reset D1CFGR register */
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RCC->D1CFGR = 0x00000000;
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/* Reset D2CFGR register */
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RCC->D2CFGR = 0x00000000;
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/* Reset D3CFGR register */
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RCC->D3CFGR = 0x00000000;
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/* Reset PLLCKSELR register */
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RCC->PLLCKSELR = 0x00000000;
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/* Reset PLL1DIVR register */
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RCC->PLL1DIVR = 0x00000000;
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/* Reset PLL1FRACR register */
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RCC->PLL1FRACR = 0x00000000;
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/* Reset PLL2DIVR register */
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RCC->PLL2DIVR = 0x00000000;
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/* Reset PLL2FRACR register */
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RCC->PLL2FRACR = 0x00000000;
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/* Reset PLL3DIVR register */
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RCC->PLL3DIVR = 0x00000000;
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/* Reset PLL3FRACR register */
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RCC->PLL3FRACR = 0x00000000;
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#endif
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/* Reset HSEBYP bit */
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RCC->CR &= (uint32_t)0xFFFBFFFF;
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/* Disable all interrupts */
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#if defined(STM32F4) || defined(STM32F7)
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RCC->CIR = 0x00000000;
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#elif defined(STM32L4) || defined(STM32H7)
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RCC->CIER = 0x00000000;
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#endif
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#if defined(STM32H7)
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/* Change the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */
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*((__IO uint32_t*)0x51008108) = 0x00000001;
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#endif
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/* Configure the Vector Table location add offset address ------------------*/
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#ifdef MICROPY_HW_VTOR
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SCB->VTOR = MICROPY_HW_VTOR;
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#else
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#ifdef VECT_TAB_SRAM
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SCB->VTOR = SRAM1_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
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#else
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SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
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#endif
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#endif
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/* dpgeorge: enable 8-byte stack alignment for IRQ handlers, in accord with EABI */
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SCB->CCR |= SCB_CCR_STKALIGN_Msk;
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}
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/**
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* @brief System Clock Configuration
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*
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* The system Clock is configured for F4/F7 as follows:
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* System Clock source = PLL (HSE)
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* SYSCLK(Hz) = 168000000
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* HCLK(Hz) = 168000000
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* AHB Prescaler = 1
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* APB1 Prescaler = 4
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* APB2 Prescaler = 2
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* HSE Frequency(Hz) = HSE_VALUE
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* PLL_M = HSE_VALUE/1000000
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* PLL_N = 336
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* PLL_P = 2
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* PLL_Q = 7
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* VDD(V) = 3.3
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* Main regulator output voltage = Scale1 mode
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* Flash Latency(WS) = 5
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*
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* The system Clock is configured for L4 as follows:
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* System Clock source = PLL (MSI)
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* SYSCLK(Hz) = 80000000
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* HCLK(Hz) = 80000000
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* AHB Prescaler = 1
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* APB1 Prescaler = 1
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* APB2 Prescaler = 1
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* MSI Frequency(Hz) = MSI_VALUE (4000000)
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* LSE Frequency(Hz) = 32768
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* PLL_M = 1
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* PLL_N = 40
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* PLL_P = 7
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* PLL_Q = 2
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* PLL_R = 2 <= This is the source for SysClk, not as on F4/7 PLL_P
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* Flash Latency(WS) = 4
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* @param None
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* @retval None
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*
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* PLL is configured as follows:
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*
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* VCO_IN
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* F4/F7 = HSE / M
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* L4 = MSI / M
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* VCO_OUT
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* F4/F7 = HSE / M * N
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* L4 = MSI / M * N
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* PLLCLK
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* F4/F7 = HSE / M * N / P
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* L4 = MSI / M * N / R
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* PLL48CK
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* F4/F7 = HSE / M * N / Q
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* L4 = MSI / M * N / Q USB Clock is obtained over PLLSAI1
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*
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* SYSCLK = PLLCLK
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* HCLK = SYSCLK / AHB_PRESC
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* PCLKx = HCLK / APBx_PRESC
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*
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* Constraints on parameters:
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*
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* VCO_IN between 1MHz and 2MHz (2MHz recommended)
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* VCO_OUT between 192MHz and 432MHz
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* HSE = 8MHz
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* M = 2 .. 63 (inclusive)
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* N = 192 ... 432 (inclusive)
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* P = 2, 4, 6, 8
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* Q = 2 .. 15 (inclusive)
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*
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* AHB_PRESC=1,2,4,8,16,64,128,256,512
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* APBx_PRESC=1,2,4,8,16
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*
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* Output clocks:
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*
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* CPU SYSCLK max 168MHz
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* USB,RNG,SDIO PLL48CK must be 48MHz for USB
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* AHB HCLK max 168MHz
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* APB1 PCLK1 max 42MHz
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* APB2 PCLK2 max 84MHz
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*
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* Timers run from APBx if APBx_PRESC=1, else 2x APBx
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*/
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void SystemClock_Config(void)
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{
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RCC_ClkInitTypeDef RCC_ClkInitStruct;
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RCC_OscInitTypeDef RCC_OscInitStruct;
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#if defined(STM32H7)
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RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
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#endif
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#if defined(STM32F4) || defined(STM32F7) || defined(STM32H7)
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/* Enable Power Control clock */
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#if defined(STM32H7)
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MODIFY_REG(PWR->CR3, PWR_CR3_SCUEN, 0);
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#else
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__PWR_CLK_ENABLE();
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#endif
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/* The voltage scaling allows optimizing the power consumption when the device is
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clocked below the maximum system frequency, to update the voltage scaling value
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regarding system frequency refer to product datasheet. */
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__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
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#elif defined(STM32L4)
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// Configure LSE Drive Capability
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__HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW);
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#endif
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#if defined(STM32H7)
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// Wait for PWR_FLAG_VOSRDY
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while ((PWR->D3CR & (PWR_D3CR_VOSRDY)) != PWR_D3CR_VOSRDY) {
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}
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#endif
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/* Enable HSE Oscillator and activate PLL with HSE as source */
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#if defined(STM32F4) || defined(STM32F7) || defined(STM32H7)
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RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
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RCC_OscInitStruct.HSEState = MICROPY_HW_CLK_HSE_STATE;
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RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
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#if defined(STM32H7)
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RCC_OscInitStruct.CSIState = RCC_CSI_OFF;
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#endif
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RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
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#elif defined(STM32L4)
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RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE|RCC_OSCILLATORTYPE_MSI;
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RCC_OscInitStruct.LSEState = RCC_LSE_ON;
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RCC_OscInitStruct.MSIState = RCC_MSI_ON;
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RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
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RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
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RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
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#endif
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
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/* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2
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clocks dividers */
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RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
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#if defined(STM32H7)
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RCC_ClkInitStruct.ClockType |= (RCC_CLOCKTYPE_D3PCLK1 | RCC_CLOCKTYPE_D1PCLK1);
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#endif
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RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
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#if defined(MICROPY_HW_CLK_LAST_FREQ) && MICROPY_HW_CLK_LAST_FREQ
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#if defined(STM32F7)
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#define FREQ_BKP BKP31R
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#elif defined(STM32L4)
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#error Unsupported Processor
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#else
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#define FREQ_BKP BKP19R
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#endif
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uint32_t m = RTC->FREQ_BKP;
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uint32_t n;
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uint32_t p;
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uint32_t q;
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// 222111HH HHQQQQPP nNNNNNNN NNMMMMMM
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uint32_t h = (m >> 22) & 0xf;
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uint32_t b1 = (m >> 26) & 0x7;
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uint32_t b2 = (m >> 29) & 0x7;
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q = (m >> 18) & 0xf;
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p = (((m >> 16) & 0x03)+1)*2;
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n = (m >> 6) & 0x3ff;
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m &= 0x3f;
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if ((q < 2) || (q > 15) || (p > 8) || (p < 2) || (n < 192) || (n >= 433) || (m < 2)) {
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m = MICROPY_HW_CLK_PLLM;
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n = MICROPY_HW_CLK_PLLN;
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p = MICROPY_HW_CLK_PLLP;
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q = MICROPY_HW_CLK_PLLQ;
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h = RCC_SYSCLK_DIV1;
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b1 = RCC_HCLK_DIV4;
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b2 = RCC_HCLK_DIV2;
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} else {
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h <<= 4;
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b1 <<= 10;
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b2 <<= 10;
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}
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RCC_OscInitStruct.PLL.PLLM = m; //MICROPY_HW_CLK_PLLM;
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RCC_OscInitStruct.PLL.PLLN = n; //MICROPY_HW_CLK_PLLN;
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RCC_OscInitStruct.PLL.PLLP = p; //MICROPY_HW_CLK_PLLP;
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RCC_OscInitStruct.PLL.PLLQ = q; //MICROPY_HW_CLK_PLLQ;
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RCC_ClkInitStruct.AHBCLKDivider = h; //RCC_SYSCLK_DIV1;
|
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RCC_ClkInitStruct.APB1CLKDivider = b1; //RCC_HCLK_DIV4;
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RCC_ClkInitStruct.APB2CLKDivider = b2; //RCC_HCLK_DIV2;
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#else // defined(MICROPY_HW_CLK_LAST_FREQ) && MICROPY_HW_CLK_LAST_FREQ
|
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RCC_OscInitStruct.PLL.PLLM = MICROPY_HW_CLK_PLLM;
|
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RCC_OscInitStruct.PLL.PLLN = MICROPY_HW_CLK_PLLN;
|
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RCC_OscInitStruct.PLL.PLLP = MICROPY_HW_CLK_PLLP;
|
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RCC_OscInitStruct.PLL.PLLQ = MICROPY_HW_CLK_PLLQ;
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#if defined(STM32L4) || defined(STM32H7)
|
|
RCC_OscInitStruct.PLL.PLLR = MICROPY_HW_CLK_PLLR;
|
|
#endif
|
|
|
|
#if defined(STM32H7)
|
|
RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_1;
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|
RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE;
|
|
RCC_OscInitStruct.PLL.PLLFRACN = 0;
|
|
#endif
|
|
|
|
#if defined(STM32F4) || defined(STM32F7)
|
|
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
|
|
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
|
|
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
|
|
#elif defined(STM32L4)
|
|
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
|
|
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
|
|
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
|
|
#elif defined(STM32H7)
|
|
RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
|
|
RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2;
|
|
RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2;
|
|
RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2;
|
|
RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2;
|
|
RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2;
|
|
#endif
|
|
#endif
|
|
|
|
if(HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
|
|
__fatal_error("HAL_RCC_OscConfig");
|
|
}
|
|
|
|
#if defined(STM32H7)
|
|
/* PLL3 for USB Clock */
|
|
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
|
|
PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLL3;
|
|
PeriphClkInitStruct.PLL3.PLL3M = 4;
|
|
PeriphClkInitStruct.PLL3.PLL3N = 120;
|
|
PeriphClkInitStruct.PLL3.PLL3P = 2;
|
|
PeriphClkInitStruct.PLL3.PLL3Q = 5;
|
|
PeriphClkInitStruct.PLL3.PLL3R = 2;
|
|
PeriphClkInitStruct.PLL3.PLL3RGE = RCC_PLL3VCIRANGE_1;
|
|
PeriphClkInitStruct.PLL3.PLL3VCOSEL = RCC_PLL3VCOWIDE;
|
|
PeriphClkInitStruct.PLL3.PLL3FRACN = 0;
|
|
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
|
|
__fatal_error("HAL_RCCEx_PeriphCLKConfig");
|
|
}
|
|
#endif
|
|
|
|
#if defined(STM32F7)
|
|
/* Activate the OverDrive to reach the 200 MHz Frequency */
|
|
if (HAL_PWREx_EnableOverDrive() != HAL_OK)
|
|
{
|
|
__fatal_error("HAL_PWREx_EnableOverDrive");
|
|
}
|
|
#endif
|
|
|
|
#if !defined(MICROPY_HW_FLASH_LATENCY)
|
|
#define MICROPY_HW_FLASH_LATENCY FLASH_LATENCY_5
|
|
#endif
|
|
|
|
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, MICROPY_HW_FLASH_LATENCY) != HAL_OK)
|
|
{
|
|
__fatal_error("HAL_RCC_ClockConfig");
|
|
}
|
|
|
|
#if defined(STM32H7)
|
|
/* Activate CSI clock mandatory for I/O Compensation Cell*/
|
|
__HAL_RCC_CSI_ENABLE() ;
|
|
|
|
/* Enable SYSCFG clock mandatory for I/O Compensation Cell */
|
|
__HAL_RCC_SYSCFG_CLK_ENABLE() ;
|
|
|
|
/* Enable the I/O Compensation Cell */
|
|
HAL_EnableCompensationCell();
|
|
|
|
/* Enable the USB voltage level detector */
|
|
HAL_PWREx_EnableUSBVoltageDetector();
|
|
#endif
|
|
|
|
#if defined(STM32F7)
|
|
// The DFU bootloader changes the clocksource register from its default power
|
|
// on reset value, so we set it back here, so the clocksources are the same
|
|
// whether we were started from DFU or from a power on reset.
|
|
|
|
RCC->DCKCFGR2 = 0;
|
|
#endif
|
|
#if defined(STM32L4)
|
|
// Enable MSI-Hardware auto calibration mode with LSE
|
|
HAL_RCCEx_EnableMSIPLLMode();
|
|
|
|
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
|
|
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SAI1|RCC_PERIPHCLK_I2C1
|
|
|RCC_PERIPHCLK_USB |RCC_PERIPHCLK_ADC
|
|
|RCC_PERIPHCLK_RNG |RCC_PERIPHCLK_RTC;
|
|
PeriphClkInitStruct.I2c1ClockSelection = RCC_I2C1CLKSOURCE_PCLK1;
|
|
/* PLLSAI is used to clock USB, ADC, I2C1 and RNG. The frequency is
|
|
HSE(8MHz)/PLLM(2)*PLLSAI1N(24)/PLLSAIQ(2) = 48MHz. See the STM32CubeMx
|
|
application or the reference manual. */
|
|
PeriphClkInitStruct.Sai1ClockSelection = RCC_SAI1CLKSOURCE_PLLSAI1;
|
|
PeriphClkInitStruct.AdcClockSelection = RCC_ADCCLKSOURCE_PLLSAI1;
|
|
PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1;
|
|
PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE;
|
|
PeriphClkInitStruct.RngClockSelection = RCC_RNGCLKSOURCE_PLLSAI1;
|
|
PeriphClkInitStruct.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_MSI;
|
|
PeriphClkInitStruct.PLLSAI1.PLLSAI1M = 1;
|
|
PeriphClkInitStruct.PLLSAI1.PLLSAI1N = 24;
|
|
PeriphClkInitStruct.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7;
|
|
PeriphClkInitStruct.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2;
|
|
PeriphClkInitStruct.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2;
|
|
PeriphClkInitStruct.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_SAI1CLK
|
|
|RCC_PLLSAI1_48M2CLK
|
|
|RCC_PLLSAI1_ADC1CLK;
|
|
|
|
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
|
|
{
|
|
__fatal_error("HAL_RCCEx_PeriphCLKConfig");
|
|
}
|
|
|
|
__PWR_CLK_ENABLE();
|
|
|
|
HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
|
|
|
|
HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/1000);
|
|
|
|
HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK);
|
|
#endif
|
|
}
|
|
|
|
void HAL_MspInit(void) {
|
|
#if defined(STM32F7) || defined(STM32H7)
|
|
/* Enable I-Cache */
|
|
SCB_EnableICache();
|
|
|
|
/* Enable D-Cache */
|
|
SCB_EnableDCache();
|
|
#endif
|
|
}
|