8f55c74533
These are core configurations providing PYBv1.x-level features.
97 lines
2.1 KiB
Plaintext
97 lines
2.1 KiB
Plaintext
/*
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Linker script for PYBD with STM32F767
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Memory layout for mboot configuration (this here describes the app part):
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FLASH_APP .isr_vector
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FLASH_APP .text
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FLASH_APP .data
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RAM .data
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RAM .bss
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RAM .heap
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RAM .stack
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*/
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/* Specify the memory areas */
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MEMORY
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{
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FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 2048K
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FLASH_ISR (rx) : ORIGIN = 0x08000000, LENGTH = 32K /* sector 0, 32K */
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FLASH_APP (rx) : ORIGIN = 0x08008000, LENGTH = 2016K /* sectors 1-11 3x32K 1*128K 7*256K */
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FLASH_EXT (rx) : ORIGIN = 0x90000000, LENGTH = 2048K /* external QSPI */
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RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 512K /* DTCM=128k, SRAM1=368K, SRAM2=16K */
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}
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/* produce a link error if there is not this amount of RAM for these sections */
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_minimum_stack_size = 2K;
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_minimum_heap_size = 16K;
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/* Define tho top end of the stack. The stack is full descending so begins just
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above last byte of RAM. Note that EABI requires the stack to be 8-byte
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aligned for a call. */
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_estack = ORIGIN(RAM) + LENGTH(RAM);
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/* RAM extents for the garbage collector */
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_ram_start = ORIGIN(RAM);
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_ram_end = ORIGIN(RAM) + LENGTH(RAM);
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_heap_start = _ebss; /* heap starts just after statically allocated memory */
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_heap_end = _ram_end - 24K; /* 24k stack */
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ENTRY(Reset_Handler)
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/* Define output sections */
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SECTIONS
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{
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.isr_vector :
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{
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. = ALIGN(4);
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KEEP(*(.isr_vector))
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. = ALIGN(4);
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} >FLASH_APP
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.text :
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{
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. = ALIGN(4);
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*(.text*)
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*(.rodata*)
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. = ALIGN(4);
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_etext = .;
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} >FLASH_APP
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_sidata = LOADADDR(.data);
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.data :
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{
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. = ALIGN(4);
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_sdata = .;
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*(.data*)
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. = ALIGN(4);
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_edata = .;
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} >RAM AT> FLASH_APP
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.bss :
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{
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. = ALIGN(4);
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_sbss = .;
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*(.bss*)
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*(COMMON)
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. = ALIGN(4);
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_ebss = .;
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} >RAM
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.heap :
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{
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. = ALIGN(4);
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. = . + _minimum_heap_size;
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. = ALIGN(4);
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} >RAM
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.stack :
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{
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. = ALIGN(4);
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. = . + _minimum_stack_size;
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. = ALIGN(4);
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} >RAM
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}
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