6839fff313
* atmel-samd: Remove ASF3. This will break builds. * atmel-samd: Add ASF4 for the SAMD21 and SAMD51. * Introduce the supervisor concept to facilitate porting. The supervisor is the code which runs individual MicroPython VMs. By splitting it out we make it more consistent and easier to find. This also adds very basic SAMD21 and SAMD51 support using the supervisor. Only the REPL currently works. This begins the work for #178.
698 lines
20 KiB
C
698 lines
20 KiB
C
/* Auto-generated config file hpl_gclk_config.h */
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#ifndef HPL_GCLK_CONFIG_H
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#define HPL_GCLK_CONFIG_H
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// <<< Use Configuration Wizard in Context Menu >>>
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// <e> Generic clock generator 0 configuration
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// <i> Indicates whether generic clock 0 configuration is enabled or not
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// <id> enable_gclk_gen_0
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#ifndef CONF_GCLK_GENERATOR_0_CONFIG
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#define CONF_GCLK_GENERATOR_0_CONFIG 1
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#endif
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// <h> Generic Clock Generator Control
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// <q> Run in Standby
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// <i> Indicates whether Run in Standby is enabled or not
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// <id> gclk_arch_gen_0_RUNSTDBY
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#ifndef CONF_GCLK_GEN_0_RUNSTDBY
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#define CONF_GCLK_GEN_0_RUNSTDBY 0
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#endif
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// <q> Divide Selection
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// <i> Indicates whether Divide Selection is enabled or not
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// <id> gclk_gen_0_div_sel
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#ifndef CONF_GCLK_GEN_0_DIVSEL
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#define CONF_GCLK_GEN_0_DIVSEL 0
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#endif
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// <q> Output Enable
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// <i> Indicates whether Output Enable is enabled or not
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// <id> gclk_arch_gen_0_oe
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#ifndef CONF_GCLK_GEN_0_OE
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#define CONF_GCLK_GEN_0_OE 1
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#endif
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// <q> Output Off Value
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// <i> Indicates whether Output Off Value is enabled or not
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// <id> gclk_arch_gen_0_oov
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#ifndef CONF_GCLK_GEN_0_OOV
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#define CONF_GCLK_GEN_0_OOV 0
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#endif
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// <q> Improve Duty Cycle
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// <i> Indicates whether Improve Duty Cycle is enabled or not
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// <id> gclk_arch_gen_0_idc
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#ifndef CONF_GCLK_GEN_0_IDC
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#define CONF_GCLK_GEN_0_IDC 0
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#endif
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// <q> Generic Clock Generator Enable
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// <i> Indicates whether Generic Clock Generator Enable is enabled or not
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// <id> gclk_arch_gen_0_enable
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#ifndef CONF_GCLK_GEN_0_GENEN
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#define CONF_GCLK_GEN_0_GENEN 1
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#endif
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// <y> Generic clock generator 0 source
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// <GCLK_GENCTRL_SRC_XOSC"> External Crystal Oscillator 0.4-32MHz (XOSC)
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// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
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// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
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// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
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// <GCLK_GENCTRL_SRC_OSC32K"> 32kHz High Accuracy Internal Oscillator (OSC32K)
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// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
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// <GCLK_GENCTRL_SRC_OSC8M"> 8MHz Internal Oscillator (OSC8M)
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// <GCLK_GENCTRL_SRC_DFLL48M"> Digital Frequency Locked Loop (DFLL48M)
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// <GCLK_GENCTRL_SRC_FDPLL"> Fractional Digital Phase Locked Loop (FDPLL96M)
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// <i> This defines the clock source for generic clock generator 0
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// <id> gclk_gen_0_oscillator
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#ifndef CONF_GCLK_GEN_0_SRC
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#define CONF_GCLK_GEN_0_SRC GCLK_GENCTRL_SRC_DFLL48M
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#endif
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// </h>
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//<h> Generic Clock Generator Division
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//<o> Generic clock generator 0 division <0x0000-0xFFFF>
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// <i>
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// <id> gclk_gen_0_div
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#ifndef CONF_GCLK_GEN_0_DIV
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#define CONF_GCLK_GEN_0_DIV 1
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#endif
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// </h>
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// </e>// <e> Generic clock generator 1 configuration
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// <i> Indicates whether generic clock 1 configuration is enabled or not
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// <id> enable_gclk_gen_1
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#ifndef CONF_GCLK_GENERATOR_1_CONFIG
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#define CONF_GCLK_GENERATOR_1_CONFIG 1
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#endif
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// <h> Generic Clock Generator Control
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// <q> Run in Standby
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// <i> Indicates whether Run in Standby is enabled or not
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// <id> gclk_arch_gen_1_RUNSTDBY
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#ifndef CONF_GCLK_GEN_1_RUNSTDBY
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#define CONF_GCLK_GEN_1_RUNSTDBY 0
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#endif
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// <q> Divide Selection
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// <i> Indicates whether Divide Selection is enabled or not
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// <id> gclk_gen_1_div_sel
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#ifndef CONF_GCLK_GEN_1_DIVSEL
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#define CONF_GCLK_GEN_1_DIVSEL 0
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#endif
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// <q> Output Enable
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// <i> Indicates whether Output Enable is enabled or not
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// <id> gclk_arch_gen_1_oe
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#ifndef CONF_GCLK_GEN_1_OE
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#define CONF_GCLK_GEN_1_OE 0
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#endif
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// <q> Output Off Value
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// <i> Indicates whether Output Off Value is enabled or not
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// <id> gclk_arch_gen_1_oov
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#ifndef CONF_GCLK_GEN_1_OOV
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#define CONF_GCLK_GEN_1_OOV 0
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#endif
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// <q> Improve Duty Cycle
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// <i> Indicates whether Improve Duty Cycle is enabled or not
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// <id> gclk_arch_gen_1_idc
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#ifndef CONF_GCLK_GEN_1_IDC
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#define CONF_GCLK_GEN_1_IDC 0
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#endif
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// <q> Generic Clock Generator Enable
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// <i> Indicates whether Generic Clock Generator Enable is enabled or not
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// <id> gclk_arch_gen_1_enable
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#ifndef CONF_GCLK_GEN_1_GENEN
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#define CONF_GCLK_GEN_1_GENEN 1
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#endif
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// <y> Generic clock generator 1 source
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// <GCLK_GENCTRL_SRC_XOSC"> External Crystal Oscillator 0.4-32MHz (XOSC)
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// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
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// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
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// <GCLK_GENCTRL_SRC_OSC32K"> 32kHz High Accuracy Internal Oscillator (OSC32K)
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// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
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// <GCLK_GENCTRL_SRC_OSC8M"> 8MHz Internal Oscillator (OSC8M)
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// <GCLK_GENCTRL_SRC_DFLL48M"> Digital Frequency Locked Loop (DFLL48M)
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// <GCLK_GENCTRL_SRC_FDPLL"> Fractional Digital Phase Locked Loop (FDPLL96M)
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// <i> This defines the clock source for generic clock generator 1
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// <id> gclk_gen_1_oscillator
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#ifndef CONF_GCLK_GEN_1_SRC
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#define CONF_GCLK_GEN_1_SRC GCLK_GENCTRL_SRC_XOSC32K
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#endif
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// </h>
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//<h> Generic Clock Generator Division
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//<o> Generic clock generator 1 division <0x0000-0xFFFF>
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// <i>
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// <id> gclk_gen_1_div
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#ifndef CONF_GCLK_GEN_1_DIV
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#define CONF_GCLK_GEN_1_DIV 1
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#endif
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// </h>
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// </e>// <e> Generic clock generator 2 configuration
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// <i> Indicates whether generic clock 2 configuration is enabled or not
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// <id> enable_gclk_gen_2
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#ifndef CONF_GCLK_GENERATOR_2_CONFIG
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#define CONF_GCLK_GENERATOR_2_CONFIG 0
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#endif
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// <h> Generic Clock Generator Control
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// <q> Run in Standby
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// <i> Indicates whether Run in Standby is enabled or not
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// <id> gclk_arch_gen_2_RUNSTDBY
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#ifndef CONF_GCLK_GEN_2_RUNSTDBY
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#define CONF_GCLK_GEN_2_RUNSTDBY 0
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#endif
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// <q> Divide Selection
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// <i> Indicates whether Divide Selection is enabled or not
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// <id> gclk_gen_2_div_sel
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#ifndef CONF_GCLK_GEN_2_DIVSEL
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#define CONF_GCLK_GEN_2_DIVSEL 0
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#endif
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// <q> Output Enable
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// <i> Indicates whether Output Enable is enabled or not
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// <id> gclk_arch_gen_2_oe
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#ifndef CONF_GCLK_GEN_2_OE
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#define CONF_GCLK_GEN_2_OE 0
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#endif
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// <q> Output Off Value
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// <i> Indicates whether Output Off Value is enabled or not
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// <id> gclk_arch_gen_2_oov
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#ifndef CONF_GCLK_GEN_2_OOV
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#define CONF_GCLK_GEN_2_OOV 0
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#endif
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// <q> Improve Duty Cycle
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// <i> Indicates whether Improve Duty Cycle is enabled or not
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// <id> gclk_arch_gen_2_idc
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#ifndef CONF_GCLK_GEN_2_IDC
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#define CONF_GCLK_GEN_2_IDC 0
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#endif
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// <q> Generic Clock Generator Enable
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// <i> Indicates whether Generic Clock Generator Enable is enabled or not
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// <id> gclk_arch_gen_2_enable
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#ifndef CONF_GCLK_GEN_2_GENEN
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#define CONF_GCLK_GEN_2_GENEN 0
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#endif
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// <y> Generic clock generator 2 source
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// <GCLK_GENCTRL_SRC_XOSC"> External Crystal Oscillator 0.4-32MHz (XOSC)
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// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
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// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
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// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
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// <GCLK_GENCTRL_SRC_OSC32K"> 32kHz High Accuracy Internal Oscillator (OSC32K)
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// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
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// <GCLK_GENCTRL_SRC_OSC8M"> 8MHz Internal Oscillator (OSC8M)
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// <GCLK_GENCTRL_SRC_DFLL48M"> Digital Frequency Locked Loop (DFLL48M)
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// <GCLK_GENCTRL_SRC_FDPLL"> Fractional Digital Phase Locked Loop (FDPLL96M)
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// <i> This defines the clock source for generic clock generator 2
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// <id> gclk_gen_2_oscillator
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#ifndef CONF_GCLK_GEN_2_SRC
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#define CONF_GCLK_GEN_2_SRC GCLK_GENCTRL_SRC_OSC32K
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#endif
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// </h>
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//<h> Generic Clock Generator Division
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//<o> Generic clock generator 2 division <0x0000-0xFFFF>
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// <i>
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// <id> gclk_gen_2_div
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#ifndef CONF_GCLK_GEN_2_DIV
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#define CONF_GCLK_GEN_2_DIV 1
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#endif
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// </h>
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// </e>// <e> Generic clock generator 3 configuration
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// <i> Indicates whether generic clock 3 configuration is enabled or not
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// <id> enable_gclk_gen_3
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#ifndef CONF_GCLK_GENERATOR_3_CONFIG
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#define CONF_GCLK_GENERATOR_3_CONFIG 0
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#endif
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// <h> Generic Clock Generator Control
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// <q> Run in Standby
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// <i> Indicates whether Run in Standby is enabled or not
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// <id> gclk_arch_gen_3_RUNSTDBY
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#ifndef CONF_GCLK_GEN_3_RUNSTDBY
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#define CONF_GCLK_GEN_3_RUNSTDBY 0
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#endif
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// <q> Divide Selection
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// <i> Indicates whether Divide Selection is enabled or not
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// <id> gclk_gen_3_div_sel
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#ifndef CONF_GCLK_GEN_3_DIVSEL
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#define CONF_GCLK_GEN_3_DIVSEL 0
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#endif
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// <q> Output Enable
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// <i> Indicates whether Output Enable is enabled or not
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// <id> gclk_arch_gen_3_oe
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#ifndef CONF_GCLK_GEN_3_OE
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#define CONF_GCLK_GEN_3_OE 0
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#endif
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// <q> Output Off Value
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// <i> Indicates whether Output Off Value is enabled or not
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// <id> gclk_arch_gen_3_oov
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#ifndef CONF_GCLK_GEN_3_OOV
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#define CONF_GCLK_GEN_3_OOV 0
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#endif
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// <q> Improve Duty Cycle
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// <i> Indicates whether Improve Duty Cycle is enabled or not
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// <id> gclk_arch_gen_3_idc
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#ifndef CONF_GCLK_GEN_3_IDC
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#define CONF_GCLK_GEN_3_IDC 0
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#endif
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// <q> Generic Clock Generator Enable
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// <i> Indicates whether Generic Clock Generator Enable is enabled or not
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// <id> gclk_arch_gen_3_enable
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#ifndef CONF_GCLK_GEN_3_GENEN
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#define CONF_GCLK_GEN_3_GENEN 0
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#endif
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// <y> Generic clock generator 3 source
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// <GCLK_GENCTRL_SRC_XOSC"> External Crystal Oscillator 0.4-32MHz (XOSC)
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// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
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// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
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// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
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// <GCLK_GENCTRL_SRC_OSC32K"> 32kHz High Accuracy Internal Oscillator (OSC32K)
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// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
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// <GCLK_GENCTRL_SRC_OSC8M"> 8MHz Internal Oscillator (OSC8M)
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// <GCLK_GENCTRL_SRC_DFLL48M"> Digital Frequency Locked Loop (DFLL48M)
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// <GCLK_GENCTRL_SRC_FDPLL"> Fractional Digital Phase Locked Loop (FDPLL96M)
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// <i> This defines the clock source for generic clock generator 3
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// <id> gclk_gen_3_oscillator
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#ifndef CONF_GCLK_GEN_3_SRC
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#define CONF_GCLK_GEN_3_SRC GCLK_GENCTRL_SRC_OSCULP32K
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#endif
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// </h>
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//<h> Generic Clock Generator Division
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//<o> Generic clock generator 3 division <0x0000-0xFFFF>
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// <i>
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// <id> gclk_gen_3_div
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#ifndef CONF_GCLK_GEN_3_DIV
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#define CONF_GCLK_GEN_3_DIV 1
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#endif
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// </h>
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// </e>// <e> Generic clock generator 4 configuration
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// <i> Indicates whether generic clock 4 configuration is enabled or not
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// <id> enable_gclk_gen_4
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#ifndef CONF_GCLK_GENERATOR_4_CONFIG
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#define CONF_GCLK_GENERATOR_4_CONFIG 0
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#endif
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// <h> Generic Clock Generator Control
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// <q> Run in Standby
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// <i> Indicates whether Run in Standby is enabled or not
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// <id> gclk_arch_gen_4_RUNSTDBY
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#ifndef CONF_GCLK_GEN_4_RUNSTDBY
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#define CONF_GCLK_GEN_4_RUNSTDBY 0
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#endif
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// <q> Divide Selection
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// <i> Indicates whether Divide Selection is enabled or not
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// <id> gclk_gen_4_div_sel
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#ifndef CONF_GCLK_GEN_4_DIVSEL
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#define CONF_GCLK_GEN_4_DIVSEL 0
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#endif
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// <q> Output Enable
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// <i> Indicates whether Output Enable is enabled or not
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// <id> gclk_arch_gen_4_oe
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#ifndef CONF_GCLK_GEN_4_OE
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#define CONF_GCLK_GEN_4_OE 0
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#endif
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// <q> Output Off Value
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// <i> Indicates whether Output Off Value is enabled or not
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// <id> gclk_arch_gen_4_oov
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#ifndef CONF_GCLK_GEN_4_OOV
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#define CONF_GCLK_GEN_4_OOV 0
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#endif
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// <q> Improve Duty Cycle
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// <i> Indicates whether Improve Duty Cycle is enabled or not
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// <id> gclk_arch_gen_4_idc
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#ifndef CONF_GCLK_GEN_4_IDC
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#define CONF_GCLK_GEN_4_IDC 0
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#endif
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// <q> Generic Clock Generator Enable
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// <i> Indicates whether Generic Clock Generator Enable is enabled or not
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// <id> gclk_arch_gen_4_enable
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#ifndef CONF_GCLK_GEN_4_GENEN
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#define CONF_GCLK_GEN_4_GENEN 0
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#endif
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// <y> Generic clock generator 4 source
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// <GCLK_GENCTRL_SRC_XOSC"> External Crystal Oscillator 0.4-32MHz (XOSC)
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// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
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// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
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// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
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// <GCLK_GENCTRL_SRC_OSC32K"> 32kHz High Accuracy Internal Oscillator (OSC32K)
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// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
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// <GCLK_GENCTRL_SRC_OSC8M"> 8MHz Internal Oscillator (OSC8M)
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// <GCLK_GENCTRL_SRC_DFLL48M"> Digital Frequency Locked Loop (DFLL48M)
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// <GCLK_GENCTRL_SRC_FDPLL"> Fractional Digital Phase Locked Loop (FDPLL96M)
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// <i> This defines the clock source for generic clock generator 4
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// <id> gclk_gen_4_oscillator
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#ifndef CONF_GCLK_GEN_4_SRC
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#define CONF_GCLK_GEN_4_SRC GCLK_GENCTRL_SRC_OSCULP32K
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#endif
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// </h>
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//<h> Generic Clock Generator Division
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//<o> Generic clock generator 4 division <0x0000-0xFFFF>
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// <i>
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// <id> gclk_gen_4_div
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#ifndef CONF_GCLK_GEN_4_DIV
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#define CONF_GCLK_GEN_4_DIV 1
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#endif
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// </h>
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// </e>// <e> Generic clock generator 5 configuration
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// <i> Indicates whether generic clock 5 configuration is enabled or not
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// <id> enable_gclk_gen_5
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#ifndef CONF_GCLK_GENERATOR_5_CONFIG
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#define CONF_GCLK_GENERATOR_5_CONFIG 0
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#endif
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// <h> Generic Clock Generator Control
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// <q> Run in Standby
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// <i> Indicates whether Run in Standby is enabled or not
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// <id> gclk_arch_gen_5_RUNSTDBY
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#ifndef CONF_GCLK_GEN_5_RUNSTDBY
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#define CONF_GCLK_GEN_5_RUNSTDBY 0
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#endif
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// <q> Divide Selection
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// <i> Indicates whether Divide Selection is enabled or not
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// <id> gclk_gen_5_div_sel
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#ifndef CONF_GCLK_GEN_5_DIVSEL
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#define CONF_GCLK_GEN_5_DIVSEL 0
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#endif
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// <q> Output Enable
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// <i> Indicates whether Output Enable is enabled or not
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// <id> gclk_arch_gen_5_oe
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#ifndef CONF_GCLK_GEN_5_OE
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#define CONF_GCLK_GEN_5_OE 0
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#endif
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// <q> Output Off Value
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// <i> Indicates whether Output Off Value is enabled or not
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// <id> gclk_arch_gen_5_oov
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#ifndef CONF_GCLK_GEN_5_OOV
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#define CONF_GCLK_GEN_5_OOV 0
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#endif
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// <q> Improve Duty Cycle
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// <i> Indicates whether Improve Duty Cycle is enabled or not
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// <id> gclk_arch_gen_5_idc
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#ifndef CONF_GCLK_GEN_5_IDC
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#define CONF_GCLK_GEN_5_IDC 0
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#endif
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// <q> Generic Clock Generator Enable
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// <i> Indicates whether Generic Clock Generator Enable is enabled or not
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// <id> gclk_arch_gen_5_enable
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#ifndef CONF_GCLK_GEN_5_GENEN
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#define CONF_GCLK_GEN_5_GENEN 0
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#endif
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// <y> Generic clock generator 5 source
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// <GCLK_GENCTRL_SRC_XOSC"> External Crystal Oscillator 0.4-32MHz (XOSC)
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// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
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// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
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// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
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// <GCLK_GENCTRL_SRC_OSC32K"> 32kHz High Accuracy Internal Oscillator (OSC32K)
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// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
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// <GCLK_GENCTRL_SRC_OSC8M"> 8MHz Internal Oscillator (OSC8M)
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// <GCLK_GENCTRL_SRC_DFLL48M"> Digital Frequency Locked Loop (DFLL48M)
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// <GCLK_GENCTRL_SRC_FDPLL"> Fractional Digital Phase Locked Loop (FDPLL96M)
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// <i> This defines the clock source for generic clock generator 5
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// <id> gclk_gen_5_oscillator
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#ifndef CONF_GCLK_GEN_5_SRC
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#define CONF_GCLK_GEN_5_SRC GCLK_GENCTRL_SRC_OSC32K
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#endif
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// </h>
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//<h> Generic Clock Generator Division
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//<o> Generic clock generator 5 division <0x0000-0xFFFF>
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// <i>
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// <id> gclk_gen_5_div
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#ifndef CONF_GCLK_GEN_5_DIV
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#define CONF_GCLK_GEN_5_DIV 1
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#endif
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// </h>
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// </e>// <e> Generic clock generator 6 configuration
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// <i> Indicates whether generic clock 6 configuration is enabled or not
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// <id> enable_gclk_gen_6
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#ifndef CONF_GCLK_GENERATOR_6_CONFIG
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#define CONF_GCLK_GENERATOR_6_CONFIG 0
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#endif
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// <h> Generic Clock Generator Control
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// <q> Run in Standby
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// <i> Indicates whether Run in Standby is enabled or not
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// <id> gclk_arch_gen_6_RUNSTDBY
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#ifndef CONF_GCLK_GEN_6_RUNSTDBY
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#define CONF_GCLK_GEN_6_RUNSTDBY 0
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#endif
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// <q> Divide Selection
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// <i> Indicates whether Divide Selection is enabled or not
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// <id> gclk_gen_6_div_sel
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#ifndef CONF_GCLK_GEN_6_DIVSEL
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#define CONF_GCLK_GEN_6_DIVSEL 0
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#endif
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// <q> Output Enable
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// <i> Indicates whether Output Enable is enabled or not
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// <id> gclk_arch_gen_6_oe
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#ifndef CONF_GCLK_GEN_6_OE
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#define CONF_GCLK_GEN_6_OE 0
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#endif
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// <q> Output Off Value
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// <i> Indicates whether Output Off Value is enabled or not
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// <id> gclk_arch_gen_6_oov
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#ifndef CONF_GCLK_GEN_6_OOV
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#define CONF_GCLK_GEN_6_OOV 0
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#endif
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// <q> Improve Duty Cycle
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// <i> Indicates whether Improve Duty Cycle is enabled or not
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// <id> gclk_arch_gen_6_idc
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#ifndef CONF_GCLK_GEN_6_IDC
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#define CONF_GCLK_GEN_6_IDC 0
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#endif
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// <q> Generic Clock Generator Enable
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// <i> Indicates whether Generic Clock Generator Enable is enabled or not
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// <id> gclk_arch_gen_6_enable
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#ifndef CONF_GCLK_GEN_6_GENEN
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#define CONF_GCLK_GEN_6_GENEN 0
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#endif
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// <y> Generic clock generator 6 source
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// <GCLK_GENCTRL_SRC_XOSC"> External Crystal Oscillator 0.4-32MHz (XOSC)
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// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
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// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
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// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
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// <GCLK_GENCTRL_SRC_OSC32K"> 32kHz High Accuracy Internal Oscillator (OSC32K)
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// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
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// <GCLK_GENCTRL_SRC_OSC8M"> 8MHz Internal Oscillator (OSC8M)
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// <GCLK_GENCTRL_SRC_DFLL48M"> Digital Frequency Locked Loop (DFLL48M)
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// <GCLK_GENCTRL_SRC_FDPLL"> Fractional Digital Phase Locked Loop (FDPLL96M)
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// <i> This defines the clock source for generic clock generator 6
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// <id> gclk_gen_6_oscillator
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#ifndef CONF_GCLK_GEN_6_SRC
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#define CONF_GCLK_GEN_6_SRC GCLK_GENCTRL_SRC_OSC32K
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#endif
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// </h>
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//<h> Generic Clock Generator Division
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//<o> Generic clock generator 6 division <0x0000-0xFFFF>
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// <i>
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// <id> gclk_gen_6_div
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#ifndef CONF_GCLK_GEN_6_DIV
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#define CONF_GCLK_GEN_6_DIV 1
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#endif
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// </h>
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// </e>// <e> Generic clock generator 7 configuration
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// <i> Indicates whether generic clock 7 configuration is enabled or not
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// <id> enable_gclk_gen_7
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#ifndef CONF_GCLK_GENERATOR_7_CONFIG
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#define CONF_GCLK_GENERATOR_7_CONFIG 0
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#endif
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// <h> Generic Clock Generator Control
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// <q> Run in Standby
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|
// <i> Indicates whether Run in Standby is enabled or not
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// <id> gclk_arch_gen_7_RUNSTDBY
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#ifndef CONF_GCLK_GEN_7_RUNSTDBY
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#define CONF_GCLK_GEN_7_RUNSTDBY 0
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#endif
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// <q> Divide Selection
|
|
// <i> Indicates whether Divide Selection is enabled or not
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// <id> gclk_gen_7_div_sel
|
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#ifndef CONF_GCLK_GEN_7_DIVSEL
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#define CONF_GCLK_GEN_7_DIVSEL 0
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#endif
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// <q> Output Enable
|
|
// <i> Indicates whether Output Enable is enabled or not
|
|
// <id> gclk_arch_gen_7_oe
|
|
#ifndef CONF_GCLK_GEN_7_OE
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|
#define CONF_GCLK_GEN_7_OE 0
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#endif
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// <q> Output Off Value
|
|
// <i> Indicates whether Output Off Value is enabled or not
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|
// <id> gclk_arch_gen_7_oov
|
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#ifndef CONF_GCLK_GEN_7_OOV
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#define CONF_GCLK_GEN_7_OOV 0
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#endif
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// <q> Improve Duty Cycle
|
|
// <i> Indicates whether Improve Duty Cycle is enabled or not
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// <id> gclk_arch_gen_7_idc
|
|
#ifndef CONF_GCLK_GEN_7_IDC
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|
#define CONF_GCLK_GEN_7_IDC 0
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#endif
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|
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// <q> Generic Clock Generator Enable
|
|
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
|
|
// <id> gclk_arch_gen_7_enable
|
|
#ifndef CONF_GCLK_GEN_7_GENEN
|
|
#define CONF_GCLK_GEN_7_GENEN 0
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#endif
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// <y> Generic clock generator 7 source
|
|
|
|
// <GCLK_GENCTRL_SRC_XOSC"> External Crystal Oscillator 0.4-32MHz (XOSC)
|
|
|
|
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
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|
|
|
// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
|
|
|
|
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
|
|
|
|
// <GCLK_GENCTRL_SRC_OSC32K"> 32kHz High Accuracy Internal Oscillator (OSC32K)
|
|
|
|
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
|
|
|
|
// <GCLK_GENCTRL_SRC_OSC8M"> 8MHz Internal Oscillator (OSC8M)
|
|
|
|
// <GCLK_GENCTRL_SRC_DFLL48M"> Digital Frequency Locked Loop (DFLL48M)
|
|
|
|
// <GCLK_GENCTRL_SRC_FDPLL"> Fractional Digital Phase Locked Loop (FDPLL96M)
|
|
|
|
// <i> This defines the clock source for generic clock generator 7
|
|
// <id> gclk_gen_7_oscillator
|
|
#ifndef CONF_GCLK_GEN_7_SRC
|
|
#define CONF_GCLK_GEN_7_SRC GCLK_GENCTRL_SRC_OSC32K
|
|
#endif
|
|
// </h>
|
|
|
|
//<h> Generic Clock Generator Division
|
|
//<o> Generic clock generator 7 division <0x0000-0xFFFF>
|
|
// <i>
|
|
// <id> gclk_gen_7_div
|
|
#ifndef CONF_GCLK_GEN_7_DIV
|
|
#define CONF_GCLK_GEN_7_DIV 1
|
|
#endif
|
|
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|
// </h>
|
|
// </e>
|
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|
// <<< end of configuration section >>>
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|
|
|
#endif // HPL_GCLK_CONFIG_H
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