339 lines
12 KiB
C
339 lines
12 KiB
C
/*
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* This file is part of the MicroPython project, http://micropython.org/
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2020-2021 Damien P. George
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* Copyright (c) 2022 Robert Hammelrath
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "py/runtime.h"
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#if MICROPY_PY_MACHINE_SPI
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#include "py/mphal.h"
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#include "extmod/machine_spi.h"
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#include "modmachine.h"
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#include "samd_soc.h"
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#include "pin_af.h"
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#include "clock_config.h"
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#define DEFAULT_SPI_BAUDRATE (1000000)
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#define DEFAULT_SPI_POLARITY (0)
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#define DEFAULT_SPI_PHASE (0)
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#define DEFAULT_SPI_BITS (8)
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#define DEFAULT_SPI_FIRSTBIT (0)
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typedef struct _machine_spi_obj_t {
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mp_obj_base_t base;
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uint8_t id;
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uint8_t polarity;
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uint8_t phase;
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uint8_t firstbit;
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uint8_t sck;
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uint8_t mosi;
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uint8_t miso;
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uint8_t new;
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uint32_t baudrate;
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sercom_pad_config_t sck_pad_config;
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sercom_pad_config_t mosi_pad_config;
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sercom_pad_config_t miso_pad_config;
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uint8_t *dest;
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size_t rxlen;
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} machine_spi_obj_t;
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extern Sercom *sercom_instance[];
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void common_spi_irq_handler(int spi_id) {
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// handle Sercom IRQ RXC
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machine_spi_obj_t *self = MP_STATE_PORT(sercom_table[spi_id]);
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// Handle IRQ
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if (self != NULL) {
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Sercom *spi = sercom_instance[self->id];
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if (spi->SPI.INTFLAG.bit.RXC != 0) {
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if (self->rxlen > 0) {
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*(self->dest)++ = spi->SPI.DATA.bit.DATA;
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self->rxlen--;
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} else {
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// Just in the unlikely case there is data but no space in the buffer
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// discard the data and clear the intflag
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uint32_t temp;
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(void)temp;
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temp = spi->SPI.DATA.bit.DATA;
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}
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}
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}
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}
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STATIC void machine_spi_print(const mp_print_t *print, mp_obj_t self_in, mp_print_kind_t kind) {
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machine_spi_obj_t *self = MP_OBJ_TO_PTR(self_in);
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mp_printf(print, "SPI(%u, baudrate=%u, firstbit=%u, polarity=%u, phase=%u, bits=8)",
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self->id, self->baudrate, self->firstbit, self->polarity, self->phase);
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}
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STATIC void machine_spi_init(mp_obj_base_t *self_in, size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
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enum { ARG_baudrate, ARG_polarity, ARG_phase, ARG_firstbit,
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ARG_sck, ARG_mosi, ARG_miso};
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static const mp_arg_t allowed_args[] = {
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{ MP_QSTR_baudrate, MP_ARG_INT, {.u_int = -1} },
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{ MP_QSTR_polarity, MP_ARG_INT, {.u_int = -1} },
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{ MP_QSTR_phase, MP_ARG_INT, {.u_int = -1} },
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{ MP_QSTR_firstbit, MP_ARG_INT, {.u_int = -1} },
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{ MP_QSTR_sck, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_rom_obj = MP_ROM_NONE} },
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{ MP_QSTR_mosi, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_rom_obj = MP_ROM_NONE} },
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{ MP_QSTR_miso, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_rom_obj = MP_ROM_NONE} },
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};
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machine_spi_obj_t *self = MP_OBJ_TO_PTR(self_in);
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// Parse args
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mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)];
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mp_arg_parse_all(n_args, pos_args, kw_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args);
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// Set baudrate if configured.
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if (args[ARG_baudrate].u_int >= 0) {
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self->baudrate = args[ARG_baudrate].u_int;
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}
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// Set polarity if configured.
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if (args[ARG_polarity].u_int >= 0) {
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self->polarity = args[ARG_polarity].u_int;
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}
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// Set phase if configured.
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if (args[ARG_phase].u_int >= 0) {
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self->phase = args[ARG_phase].u_int;
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}
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// Set firstbit if configured.
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if (args[ARG_firstbit].u_int >= 0) {
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self->firstbit = args[ARG_firstbit].u_int;
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}
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// Set SCK/MOSI/MISO pins if configured.
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if (args[ARG_sck].u_obj != mp_const_none) {
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self->sck = mp_hal_get_pin_obj(args[ARG_sck].u_obj);
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}
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if (args[ARG_mosi].u_obj != mp_const_none) {
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self->mosi = mp_hal_get_pin_obj(args[ARG_mosi].u_obj);
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}
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if (args[ARG_miso].u_obj != mp_const_none) {
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self->miso = mp_hal_get_pin_obj(args[ARG_miso].u_obj);
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}
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// Initialise the SPI peripheral if any arguments given, or it was not initialised previously.
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if (n_args > 0 || kw_args->used > 0 || self->new) {
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self->new = false;
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// Get the pad and alt-fct numbers.
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self->sck_pad_config = get_sercom_config(self->sck, self->id);
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self->mosi_pad_config = get_sercom_config(self->mosi, self->id);
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uint8_t dopo = 0;
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#if defined(MCU_SAMD21)
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if (self->mosi_pad_config.pad_nr == 0 && self->sck_pad_config.pad_nr == 1) {
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dopo = 0;
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} else if (self->mosi_pad_config.pad_nr == 2 && self->sck_pad_config.pad_nr == 3) {
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dopo = 1;
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} else if (self->mosi_pad_config.pad_nr == 3 && self->sck_pad_config.pad_nr == 1) {
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dopo = 2;
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} else if (self->mosi_pad_config.pad_nr == 0 && self->sck_pad_config.pad_nr == 3) {
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dopo = 3;
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} else {
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mp_raise_ValueError(MP_ERROR_TEXT("invalid pin for sck or mosi"));
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}
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#elif defined(MCU_SAMD51)
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if (self->mosi_pad_config.pad_nr == 0 && self->sck_pad_config.pad_nr == 1) {
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dopo = 0;
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} else if (self->mosi_pad_config.pad_nr == 3 && self->sck_pad_config.pad_nr == 1) {
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dopo = 2;
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} else {
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mp_raise_ValueError(MP_ERROR_TEXT("invalid pin for sck or mosi"));
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}
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#endif
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if (self->miso != 0xff) { // Miso may be undefined
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self->miso_pad_config = get_sercom_config(self->miso, self->id);
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mp_hal_set_pin_mux(self->miso, self->miso_pad_config.alt_fct);
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}
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// Configure the Pin mux.
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mp_hal_set_pin_mux(self->sck, self->sck_pad_config.alt_fct);
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mp_hal_set_pin_mux(self->mosi, self->mosi_pad_config.alt_fct);
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// Set up the clocks
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enable_sercom_clock(self->id);
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// Configure the SPI
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Sercom *spi = sercom_instance[self->id];
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// Reset (clear) the peripheral registers.
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while (spi->SPI.SYNCBUSY.bit.SWRST) {
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}
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spi->SPI.CTRLA.bit.SWRST = 1;
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while (spi->SPI.SYNCBUSY.bit.SWRST) {
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}
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// Set the registers
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spi->SPI.CTRLA.bit.MODE = 0x03; // SPI master mode
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spi->SPI.CTRLA.bit.CPOL = self->polarity;
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spi->SPI.CTRLA.bit.CPHA = self->phase;
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spi->SPI.CTRLA.bit.DIPO = self->miso_pad_config.pad_nr;
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spi->SPI.CTRLA.bit.DOPO = dopo;
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spi->SPI.CTRLA.bit.DORD = self->firstbit;
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// Enable receive only if miso is defined
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if (self->miso != 0xff) {
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spi->SPI.CTRLB.reg = SERCOM_SPI_CTRLB_RXEN;
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while (spi->SPI.SYNCBUSY.bit.CTRLB) {
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}
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}
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#if defined(MCU_SAMD51)
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spi->SPI.CTRLC.reg = 1; // 1 clock cycle character spacing
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#endif
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// SPI is driven by the clock of GCLK Generator 2, freq by get_peripheral_freq()
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// baud = bus_freq / (2 * baudrate) - 1
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uint32_t baud = get_peripheral_freq() / (2 * self->baudrate);
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if (baud > 0) { // Avoid underflow
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baud -= 1;
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}
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if (baud > 255) { // Avoid overflow
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baud = 255;
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}
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spi->SPI.BAUD.reg = baud; // Set Baud
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// Enable RXC interrupt only if miso is defined
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if (self->miso != 0xff) {
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#if defined(MCU_SAMD21)
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NVIC_EnableIRQ(SERCOM0_IRQn + self->id);
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#elif defined(MCU_SAMD51)
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NVIC_EnableIRQ(SERCOM0_0_IRQn + 4 * self->id + 2);
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#endif
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sercom_register_irq(self->id, &common_spi_irq_handler);
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}
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sercom_enable(spi, 1);
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}
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}
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STATIC mp_obj_t machine_spi_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *args) {
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mp_arg_check_num(n_args, n_kw, 1, MP_OBJ_FUN_ARGS_MAX, true);
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// Get SPI bus.
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int spi_id = mp_obj_get_int(args[0]);
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if (spi_id < 0 || spi_id > SERCOM_INST_NUM) {
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mp_raise_msg_varg(&mp_type_ValueError, MP_ERROR_TEXT("SPI(%d) doesn't exist"), spi_id);
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}
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// Create the SPI object and fill it with defaults.
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machine_spi_obj_t *self = mp_obj_malloc(machine_spi_obj_t, &machine_spi_type);
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self->id = spi_id;
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self->baudrate = DEFAULT_SPI_BAUDRATE;
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self->polarity = DEFAULT_SPI_POLARITY;
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self->phase = DEFAULT_SPI_PHASE;
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self->firstbit = DEFAULT_SPI_FIRSTBIT;
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self->mosi = 0xff; // 0xff: pin not defined (yet)
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self->miso = 0xff;
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self->sck = 0xff;
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self->new = true;
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MP_STATE_PORT(sercom_table[spi_id]) = self;
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mp_map_t kw_args;
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mp_map_init_fixed_table(&kw_args, n_kw, args + n_args);
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machine_spi_init((mp_obj_base_t *)self, n_args - 1, args + 1, &kw_args);
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return self;
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}
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STATIC void machine_sercom_deinit(mp_obj_base_t *self_in) {
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machine_spi_obj_t *self = MP_OBJ_TO_PTR(self_in);
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Sercom *spi = sercom_instance[self->id];
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// Disable interrupts (if any)
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spi->SPI.INTENCLR.reg = 0xff;
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sercom_enable(spi, 0);
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// clear table entry of spi
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MP_STATE_PORT(sercom_table[self->id]) = NULL;
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}
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STATIC void machine_spi_transfer(mp_obj_base_t *self_in, size_t len, const uint8_t *src, uint8_t *dest) {
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machine_spi_obj_t *self = (machine_spi_obj_t *)self_in;
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Sercom *spi = sercom_instance[self->id];
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size_t txlen = len;
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// Clear the input queue, if needed
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while (dest && spi->SPI.INTFLAG.bit.RXC) {
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uint32_t temp;
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(void)temp;
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temp = spi->SPI.DATA.bit.DATA;
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}
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// Set up the irq data pointers and enable IRQ
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if (dest) {
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if (self->miso == 0xff) {
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mp_raise_ValueError(MP_ERROR_TEXT("read is not enabled"));
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}
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spi->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_RXC;
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self->dest = dest;
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self->rxlen = len;
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}
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// Send by polling & receive by IRQ
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while (txlen) {
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if (spi->SPI.INTFLAG.bit.DRE) {
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spi->SPI.DATA.bit.DATA = *src;
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src += 1;
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txlen--;
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}
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}
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// Receive the remaining data, if any and clear IRQ
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// Do no wait forever.
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if (dest) {
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int32_t timeout = 1000;
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while (self->rxlen > 0 && timeout) {
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timeout--;
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MICROPY_EVENT_POLL_HOOK
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}
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spi->SPI.INTENCLR.reg = SERCOM_SPI_INTENCLR_RXC;
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} else {
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// Wait for the data being shifted out.
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while (!spi->SPI.INTFLAG.bit.TXC) {
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}
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}
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}
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STATIC const mp_machine_spi_p_t machine_spi_p = {
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.init = machine_spi_init,
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.deinit = machine_sercom_deinit,
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.transfer = machine_spi_transfer,
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};
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MP_DEFINE_CONST_OBJ_TYPE(
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machine_spi_type,
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MP_QSTR_SPI,
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MP_TYPE_FLAG_NONE,
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make_new, machine_spi_make_new,
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print, machine_spi_print,
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protocol, &machine_spi_p,
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locals_dict, &mp_machine_spi_locals_dict
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);
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#endif
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