circuitpython/ports/mimxrt10xx/common-hal
Scott Shawcroft 7d8dac9211
Refine iMX RT memory layout and add three boards
Introduces a way to place CircuitPython code and data into
tightly coupled memory (TCM) which is accessible by the CPU in a
single cycle. It also frees up room in the corresponding cache for
intermittent data. Loading from external flash is slow!

The data cache is also now enabled.

Adds support for the iMX RT 1021 chip. Adds three new boards:
* iMX RT 1020 EVK
* iMX RT 1060 EVK
* Teensy 4.0

Related to #2492, #2472 and #2477. Fixes #2475.
2020-01-17 17:36:08 -08:00
..
analogio mimxrt10xx: Use the correct error for not implemented functionality 2020-01-07 09:29:47 +01:00
board Add initial MIMXRT10XX port 2020-01-06 21:08:49 +01:00
busio add flag to i.mx port 2020-01-10 09:20:21 -05:00
digitalio Add initial MIMXRT10XX port 2020-01-06 21:08:49 +01:00
microcontroller Refine iMX RT memory layout and add three boards 2020-01-17 17:36:08 -08:00
neopixel_write Add initial MIMXRT10XX port 2020-01-06 21:08:49 +01:00
os Add initial MIMXRT10XX port 2020-01-06 21:08:49 +01:00
pulseio Add initial MIMXRT10XX port 2020-01-06 21:08:49 +01:00
rtc Add initial MIMXRT10XX port 2020-01-06 21:08:49 +01:00
supervisor Add initial MIMXRT10XX port 2020-01-06 21:08:49 +01:00
time Add initial MIMXRT10XX port 2020-01-06 21:08:49 +01:00