86fe73beb9
This patch removes the global cache variables from the SPI flash driver and now requires the user to provide the cache memory themselves, via the SPI flash configuration struct. This allows to either have a shared cache for multiple SPI flash devices (by sharing a mp_spiflash_cache_t struct), or have a single cache per device (or a mix of these options). To configure the cache use: mp_spiflash_cache_t spi_bdev_cache; const mp_spiflash_config_t spiflash_config = // any bus options .cache = &spi_bdev_cache, };
445 lines
14 KiB
C
445 lines
14 KiB
C
/*
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* This file is part of the MicroPython project, http://micropython.org/
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2016-2018 Damien P. George
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include <stdio.h>
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#include <string.h>
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#include "py/mperrno.h"
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#include "py/mphal.h"
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#include "drivers/memory/spiflash.h"
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#define QSPI_QE_MASK (0x02)
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#define USE_WR_DELAY (1)
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#define CMD_WRSR (0x01)
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#define CMD_WRITE (0x02)
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#define CMD_READ (0x03)
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#define CMD_RDSR (0x05)
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#define CMD_WREN (0x06)
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#define CMD_SEC_ERASE (0x20)
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#define CMD_RDCR (0x35)
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#define CMD_RD_DEVID (0x9f)
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#define CMD_CHIP_ERASE (0xc7)
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#define CMD_C4READ (0xeb)
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#define WAIT_SR_TIMEOUT (1000000)
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#define PAGE_SIZE (256) // maximum bytes we can write in one SPI transfer
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#define SECTOR_SIZE MP_SPIFLASH_ERASE_BLOCK_SIZE
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STATIC void mp_spiflash_acquire_bus(mp_spiflash_t *self) {
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const mp_spiflash_config_t *c = self->config;
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if (c->bus_kind == MP_SPIFLASH_BUS_QSPI) {
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c->bus.u_qspi.proto->ioctl(c->bus.u_qspi.data, MP_QSPI_IOCTL_BUS_ACQUIRE);
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}
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}
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STATIC void mp_spiflash_release_bus(mp_spiflash_t *self) {
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const mp_spiflash_config_t *c = self->config;
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if (c->bus_kind == MP_SPIFLASH_BUS_QSPI) {
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c->bus.u_qspi.proto->ioctl(c->bus.u_qspi.data, MP_QSPI_IOCTL_BUS_RELEASE);
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}
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}
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STATIC void mp_spiflash_write_cmd_data(mp_spiflash_t *self, uint8_t cmd, size_t len, uint32_t data) {
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const mp_spiflash_config_t *c = self->config;
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if (c->bus_kind == MP_SPIFLASH_BUS_SPI) {
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// Note: len/data are unused for standard SPI
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mp_hal_pin_write(c->bus.u_spi.cs, 0);
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c->bus.u_spi.proto->transfer(c->bus.u_spi.data, 1, &cmd, NULL);
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mp_hal_pin_write(c->bus.u_spi.cs, 1);
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} else {
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c->bus.u_qspi.proto->write_cmd_data(c->bus.u_qspi.data, cmd, len, data);
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}
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}
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STATIC void mp_spiflash_write_cmd_addr_data(mp_spiflash_t *self, uint8_t cmd, uint32_t addr, size_t len, const uint8_t *src) {
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const mp_spiflash_config_t *c = self->config;
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if (c->bus_kind == MP_SPIFLASH_BUS_SPI) {
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uint8_t buf[4] = {cmd, addr >> 16, addr >> 8, addr};
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mp_hal_pin_write(c->bus.u_spi.cs, 0);
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c->bus.u_spi.proto->transfer(c->bus.u_spi.data, 4, buf, NULL);
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if (len) {
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c->bus.u_spi.proto->transfer(c->bus.u_spi.data, len, src, NULL);
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}
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mp_hal_pin_write(c->bus.u_spi.cs, 1);
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} else {
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c->bus.u_qspi.proto->write_cmd_addr_data(c->bus.u_qspi.data, cmd, addr, len, src);
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}
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}
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STATIC uint32_t mp_spiflash_read_cmd(mp_spiflash_t *self, uint8_t cmd, size_t len) {
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const mp_spiflash_config_t *c = self->config;
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if (c->bus_kind == MP_SPIFLASH_BUS_SPI) {
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uint32_t buf;
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mp_hal_pin_write(c->bus.u_spi.cs, 0);
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c->bus.u_spi.proto->transfer(c->bus.u_spi.data, 1, &cmd, NULL);
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c->bus.u_spi.proto->transfer(c->bus.u_spi.data, len, (void*)&buf, (void*)&buf);
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mp_hal_pin_write(c->bus.u_spi.cs, 1);
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return buf;
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} else {
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return c->bus.u_qspi.proto->read_cmd(c->bus.u_qspi.data, cmd, len);
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}
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}
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STATIC void mp_spiflash_read_data(mp_spiflash_t *self, uint32_t addr, size_t len, uint8_t *dest) {
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const mp_spiflash_config_t *c = self->config;
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if (c->bus_kind == MP_SPIFLASH_BUS_SPI) {
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uint8_t buf[4] = {CMD_READ, addr >> 16, addr >> 8, addr};
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mp_hal_pin_write(c->bus.u_spi.cs, 0);
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c->bus.u_spi.proto->transfer(c->bus.u_spi.data, 4, buf, NULL);
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c->bus.u_spi.proto->transfer(c->bus.u_spi.data, len, dest, dest);
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mp_hal_pin_write(c->bus.u_spi.cs, 1);
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} else {
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c->bus.u_qspi.proto->read_cmd_qaddr_qdata(c->bus.u_qspi.data, CMD_C4READ, addr, len, dest);
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}
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}
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STATIC void mp_spiflash_write_cmd(mp_spiflash_t *self, uint8_t cmd) {
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mp_spiflash_write_cmd_data(self, cmd, 0, 0);
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}
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STATIC void mp_spiflash_write_cmd_addr(mp_spiflash_t *self, uint8_t cmd, uint32_t addr) {
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mp_spiflash_write_cmd_addr_data(self, cmd, addr, 0, NULL);
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}
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STATIC int mp_spiflash_wait_sr(mp_spiflash_t *self, uint8_t mask, uint8_t val, uint32_t timeout) {
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uint8_t sr;
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for (; timeout; --timeout) {
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sr = mp_spiflash_read_cmd(self, CMD_RDSR, 1);
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if ((sr & mask) == val) {
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break;
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}
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}
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if ((sr & mask) == val) {
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return 0; // success
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} else if (timeout == 0) {
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return -MP_ETIMEDOUT;
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} else {
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return -MP_EIO;
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}
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}
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STATIC int mp_spiflash_wait_wel1(mp_spiflash_t *self) {
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return mp_spiflash_wait_sr(self, 2, 2, WAIT_SR_TIMEOUT);
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}
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STATIC int mp_spiflash_wait_wip0(mp_spiflash_t *self) {
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return mp_spiflash_wait_sr(self, 1, 0, WAIT_SR_TIMEOUT);
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}
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void mp_spiflash_init(mp_spiflash_t *self) {
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self->flags = 0;
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if (self->config->bus_kind == MP_SPIFLASH_BUS_SPI) {
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mp_hal_pin_write(self->config->bus.u_spi.cs, 1);
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mp_hal_pin_output(self->config->bus.u_spi.cs);
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self->config->bus.u_spi.proto->ioctl(self->config->bus.u_spi.data, MP_SPI_IOCTL_INIT);
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} else {
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self->config->bus.u_qspi.proto->ioctl(self->config->bus.u_qspi.data, MP_QSPI_IOCTL_INIT);
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}
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mp_spiflash_acquire_bus(self);
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#if defined(CHECK_DEVID)
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// Validate device id
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uint32_t devid = mp_spiflash_read_cmd(self, CMD_RD_DEVID, 3);
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if (devid != CHECK_DEVID) {
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return 0;
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}
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#endif
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if (self->config->bus_kind == MP_SPIFLASH_BUS_QSPI) {
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// Set QE bit
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uint32_t data = (mp_spiflash_read_cmd(self, CMD_RDSR, 1) & 0xff)
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| (mp_spiflash_read_cmd(self, CMD_RDCR, 1) & 0xff) << 8;
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if (!(data & (QSPI_QE_MASK << 8))) {
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data |= QSPI_QE_MASK << 8;
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mp_spiflash_write_cmd(self, CMD_WREN);
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mp_spiflash_write_cmd_data(self, CMD_WRSR, 2, data);
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mp_spiflash_wait_wip0(self);
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}
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}
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mp_spiflash_release_bus(self);
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}
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STATIC int mp_spiflash_erase_sector(mp_spiflash_t *self, uint32_t addr) {
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// enable writes
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mp_spiflash_write_cmd(self, CMD_WREN);
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// wait WEL=1
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int ret = mp_spiflash_wait_wel1(self);
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if (ret != 0) {
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return ret;
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}
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// erase the sector
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mp_spiflash_write_cmd_addr(self, CMD_SEC_ERASE, addr);
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// wait WIP=0
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return mp_spiflash_wait_wip0(self);
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}
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STATIC int mp_spiflash_write_page(mp_spiflash_t *self, uint32_t addr, const uint8_t *src) {
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// enable writes
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mp_spiflash_write_cmd(self, CMD_WREN);
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// wait WEL=1
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int ret = mp_spiflash_wait_wel1(self);
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if (ret != 0) {
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return ret;
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}
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// write the page
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mp_spiflash_write_cmd_addr_data(self, CMD_WRITE, addr, PAGE_SIZE, src);
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// wait WIP=0
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return mp_spiflash_wait_wip0(self);
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}
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void mp_spiflash_read(mp_spiflash_t *self, uint32_t addr, size_t len, uint8_t *dest) {
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if (len == 0) {
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return;
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}
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mp_spiflash_acquire_bus(self);
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mp_spiflash_cache_t *cache = self->config->cache;
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if (cache->user == self && cache->block != 0xffffffff) {
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uint32_t bis = addr / SECTOR_SIZE;
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uint32_t bie = (addr + len - 1) / SECTOR_SIZE;
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if (bis <= cache->block && cache->block <= bie) {
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// Read straddles current buffer
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size_t rest = 0;
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if (bis < cache->block) {
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// Read direct from flash for first part
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rest = cache->block * SECTOR_SIZE - addr;
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mp_spiflash_read_data(self, addr, rest, dest);
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len -= rest;
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dest += rest;
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addr += rest;
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}
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uint32_t offset = addr & (SECTOR_SIZE - 1);
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rest = SECTOR_SIZE - offset;
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if (rest > len) {
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rest = len;
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}
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memcpy(dest, &cache->buf[offset], rest);
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len -= rest;
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if (len == 0) {
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mp_spiflash_release_bus(self);
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return;
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}
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dest += rest;
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addr += rest;
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}
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}
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// Read rest direct from flash
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mp_spiflash_read_data(self, addr, len, dest);
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mp_spiflash_release_bus(self);
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}
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STATIC void mp_spiflash_flush_internal(mp_spiflash_t *self) {
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#if USE_WR_DELAY
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if (!(self->flags & 1)) {
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return;
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}
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self->flags &= ~1;
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mp_spiflash_cache_t *cache = self->config->cache;
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// Erase sector
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int ret = mp_spiflash_erase_sector(self, cache->block * SECTOR_SIZE);
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if (ret != 0) {
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return;
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}
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// Write
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for (int i = 0; i < 16; i += 1) {
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int ret = mp_spiflash_write_page(self, cache->block * SECTOR_SIZE + i * PAGE_SIZE, cache->buf + i * PAGE_SIZE);
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if (ret != 0) {
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return;
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}
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}
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#endif
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}
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void mp_spiflash_flush(mp_spiflash_t *self) {
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mp_spiflash_acquire_bus(self);
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mp_spiflash_flush_internal(self);
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mp_spiflash_release_bus(self);
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}
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STATIC int mp_spiflash_write_part(mp_spiflash_t *self, uint32_t addr, size_t len, const uint8_t *src) {
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// Align to 4096 sector
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uint32_t offset = addr & 0xfff;
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uint32_t sec = addr >> 12;
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addr = sec << 12;
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// Restriction for now, so we don't need to erase multiple pages
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if (offset + len > SECTOR_SIZE) {
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printf("mp_spiflash_write_part: len is too large\n");
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return -MP_EIO;
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}
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mp_spiflash_cache_t *cache = self->config->cache;
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// Acquire the sector buffer
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if (cache->user != self) {
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if (cache->user != NULL) {
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mp_spiflash_flush(cache->user);
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}
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cache->user = self;
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cache->block = 0xffffffff;
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}
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if (cache->block != sec) {
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// Read sector
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#if USE_WR_DELAY
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if (cache->block != 0xffffffff) {
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mp_spiflash_flush_internal(self);
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}
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#endif
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mp_spiflash_read_data(self, addr, SECTOR_SIZE, cache->buf);
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}
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#if USE_WR_DELAY
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cache->block = sec;
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// Just copy to buffer
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memcpy(cache->buf + offset, src, len);
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// And mark dirty
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self->flags |= 1;
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#else
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uint32_t dirty = 0;
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for (size_t i = 0; i < len; ++i) {
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if (cache->buf[offset + i] != src[i]) {
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if (cache->buf[offset + i] != 0xff) {
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// Erase sector
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int ret = mp_spiflash_erase_sector(self, addr);
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if (ret != 0) {
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return ret;
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}
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dirty = 0xffff;
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break;
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} else {
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dirty |= (1 << ((offset + i) >> 8));
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}
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}
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}
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cache->block = sec;
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// Copy new block into buffer
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memcpy(cache->buf + offset, src, len);
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// Write sector in pages of 256 bytes
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for (size_t i = 0; i < 16; ++i) {
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if (dirty & (1 << i)) {
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int ret = mp_spiflash_write_page(self, addr + i * PAGE_SIZE, cache->buf + i * PAGE_SIZE);
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if (ret != 0) {
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return ret;
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}
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}
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}
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#endif
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return 0; // success
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}
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int mp_spiflash_write(mp_spiflash_t *self, uint32_t addr, size_t len, const uint8_t *src) {
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uint32_t bis = addr / SECTOR_SIZE;
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uint32_t bie = (addr + len - 1) / SECTOR_SIZE;
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mp_spiflash_acquire_bus(self);
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mp_spiflash_cache_t *cache = self->config->cache;
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if (cache->user == self && bis <= cache->block && bie >= cache->block) {
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// Write straddles current buffer
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uint32_t pre;
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uint32_t offset;
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if (cache->block * SECTOR_SIZE >= addr) {
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pre = cache->block * SECTOR_SIZE - addr;
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offset = 0;
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} else {
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pre = 0;
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offset = addr - cache->block * SECTOR_SIZE;
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}
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// Write buffered part first
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uint32_t len_in_buf = len - pre;
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len = 0;
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if (len_in_buf > SECTOR_SIZE - offset) {
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len = len_in_buf - (SECTOR_SIZE - offset);
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len_in_buf = SECTOR_SIZE - offset;
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}
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memcpy(&cache->buf[offset], &src[pre], len_in_buf);
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self->flags |= 1; // Mark dirty
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// Write part before buffer sector
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while (pre) {
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int rest = pre & (SECTOR_SIZE - 1);
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if (rest == 0) {
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rest = SECTOR_SIZE;
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}
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int ret = mp_spiflash_write_part(self, addr, rest, src);
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if (ret != 0) {
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mp_spiflash_release_bus(self);
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return ret;
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}
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src += rest;
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addr += rest;
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pre -= rest;
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}
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src += len_in_buf;
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addr += len_in_buf;
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// Fall through to write remaining part
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}
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uint32_t offset = addr & (SECTOR_SIZE - 1);
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while (len) {
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int rest = SECTOR_SIZE - offset;
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if (rest > len) {
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rest = len;
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}
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int ret = mp_spiflash_write_part(self, addr, rest, src);
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if (ret != 0) {
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mp_spiflash_release_bus(self);
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return ret;
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}
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len -= rest;
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addr += rest;
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src += rest;
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offset = 0;
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}
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mp_spiflash_release_bus(self);
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return 0;
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}
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