6839fff313
* atmel-samd: Remove ASF3. This will break builds. * atmel-samd: Add ASF4 for the SAMD21 and SAMD51. * Introduce the supervisor concept to facilitate porting. The supervisor is the code which runs individual MicroPython VMs. By splitting it out we make it more consistent and easier to find. This also adds very basic SAMD21 and SAMD51 support using the supervisor. Only the REPL currently works. This begins the work for #178.
106 lines
6.8 KiB
C
106 lines
6.8 KiB
C
/**
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* \file
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*
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* \brief Instance description for TCC2
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*
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* Copyright (c) 2017 Atmel Corporation,
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* a wholly owned subsidiary of Microchip Technology Inc.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the Licence at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* \asf_license_stop
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*
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*/
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#ifndef _SAMD51_TCC2_INSTANCE_
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#define _SAMD51_TCC2_INSTANCE_
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/* ========== Register definition for TCC2 peripheral ========== */
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#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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#define REG_TCC2_CTRLA (0x42000C00) /**< \brief (TCC2) Control A */
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#define REG_TCC2_CTRLBCLR (0x42000C04) /**< \brief (TCC2) Control B Clear */
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#define REG_TCC2_CTRLBSET (0x42000C05) /**< \brief (TCC2) Control B Set */
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#define REG_TCC2_SYNCBUSY (0x42000C08) /**< \brief (TCC2) Synchronization Busy */
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#define REG_TCC2_FCTRLA (0x42000C0C) /**< \brief (TCC2) Recoverable Fault A Configuration */
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#define REG_TCC2_FCTRLB (0x42000C10) /**< \brief (TCC2) Recoverable Fault B Configuration */
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#define REG_TCC2_WEXCTRL (0x42000C14) /**< \brief (TCC2) Waveform Extension Configuration */
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#define REG_TCC2_DRVCTRL (0x42000C18) /**< \brief (TCC2) Driver Control */
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#define REG_TCC2_DBGCTRL (0x42000C1E) /**< \brief (TCC2) Debug Control */
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#define REG_TCC2_EVCTRL (0x42000C20) /**< \brief (TCC2) Event Control */
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#define REG_TCC2_INTENCLR (0x42000C24) /**< \brief (TCC2) Interrupt Enable Clear */
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#define REG_TCC2_INTENSET (0x42000C28) /**< \brief (TCC2) Interrupt Enable Set */
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#define REG_TCC2_INTFLAG (0x42000C2C) /**< \brief (TCC2) Interrupt Flag Status and Clear */
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#define REG_TCC2_STATUS (0x42000C30) /**< \brief (TCC2) Status */
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#define REG_TCC2_COUNT (0x42000C34) /**< \brief (TCC2) Count */
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#define REG_TCC2_WAVE (0x42000C3C) /**< \brief (TCC2) Waveform Control */
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#define REG_TCC2_PER (0x42000C40) /**< \brief (TCC2) Period */
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#define REG_TCC2_CC0 (0x42000C44) /**< \brief (TCC2) Compare and Capture 0 */
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#define REG_TCC2_CC1 (0x42000C48) /**< \brief (TCC2) Compare and Capture 1 */
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#define REG_TCC2_CC2 (0x42000C4C) /**< \brief (TCC2) Compare and Capture 2 */
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#define REG_TCC2_PERBUF (0x42000C6C) /**< \brief (TCC2) Period Buffer */
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#define REG_TCC2_CCBUF0 (0x42000C70) /**< \brief (TCC2) Compare and Capture Buffer 0 */
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#define REG_TCC2_CCBUF1 (0x42000C74) /**< \brief (TCC2) Compare and Capture Buffer 1 */
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#define REG_TCC2_CCBUF2 (0x42000C78) /**< \brief (TCC2) Compare and Capture Buffer 2 */
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#else
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#define REG_TCC2_CTRLA (*(RwReg *)0x42000C00UL) /**< \brief (TCC2) Control A */
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#define REG_TCC2_CTRLBCLR (*(RwReg8 *)0x42000C04UL) /**< \brief (TCC2) Control B Clear */
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#define REG_TCC2_CTRLBSET (*(RwReg8 *)0x42000C05UL) /**< \brief (TCC2) Control B Set */
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#define REG_TCC2_SYNCBUSY (*(RoReg *)0x42000C08UL) /**< \brief (TCC2) Synchronization Busy */
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#define REG_TCC2_FCTRLA (*(RwReg *)0x42000C0CUL) /**< \brief (TCC2) Recoverable Fault A Configuration */
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#define REG_TCC2_FCTRLB (*(RwReg *)0x42000C10UL) /**< \brief (TCC2) Recoverable Fault B Configuration */
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#define REG_TCC2_WEXCTRL (*(RwReg *)0x42000C14UL) /**< \brief (TCC2) Waveform Extension Configuration */
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#define REG_TCC2_DRVCTRL (*(RwReg *)0x42000C18UL) /**< \brief (TCC2) Driver Control */
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#define REG_TCC2_DBGCTRL (*(RwReg8 *)0x42000C1EUL) /**< \brief (TCC2) Debug Control */
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#define REG_TCC2_EVCTRL (*(RwReg *)0x42000C20UL) /**< \brief (TCC2) Event Control */
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#define REG_TCC2_INTENCLR (*(RwReg *)0x42000C24UL) /**< \brief (TCC2) Interrupt Enable Clear */
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#define REG_TCC2_INTENSET (*(RwReg *)0x42000C28UL) /**< \brief (TCC2) Interrupt Enable Set */
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#define REG_TCC2_INTFLAG (*(RwReg *)0x42000C2CUL) /**< \brief (TCC2) Interrupt Flag Status and Clear */
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#define REG_TCC2_STATUS (*(RwReg *)0x42000C30UL) /**< \brief (TCC2) Status */
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#define REG_TCC2_COUNT (*(RwReg *)0x42000C34UL) /**< \brief (TCC2) Count */
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#define REG_TCC2_WAVE (*(RwReg *)0x42000C3CUL) /**< \brief (TCC2) Waveform Control */
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#define REG_TCC2_PER (*(RwReg *)0x42000C40UL) /**< \brief (TCC2) Period */
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#define REG_TCC2_CC0 (*(RwReg *)0x42000C44UL) /**< \brief (TCC2) Compare and Capture 0 */
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#define REG_TCC2_CC1 (*(RwReg *)0x42000C48UL) /**< \brief (TCC2) Compare and Capture 1 */
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#define REG_TCC2_CC2 (*(RwReg *)0x42000C4CUL) /**< \brief (TCC2) Compare and Capture 2 */
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#define REG_TCC2_PERBUF (*(RwReg *)0x42000C6CUL) /**< \brief (TCC2) Period Buffer */
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#define REG_TCC2_CCBUF0 (*(RwReg *)0x42000C70UL) /**< \brief (TCC2) Compare and Capture Buffer 0 */
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#define REG_TCC2_CCBUF1 (*(RwReg *)0x42000C74UL) /**< \brief (TCC2) Compare and Capture Buffer 1 */
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#define REG_TCC2_CCBUF2 (*(RwReg *)0x42000C78UL) /**< \brief (TCC2) Compare and Capture Buffer 2 */
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#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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/* ========== Instance parameters for TCC2 peripheral ========== */
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#define TCC2_CC_NUM 3 // Number of Compare/Capture units
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#define TCC2_DITHERING 0 // Dithering feature implemented
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#define TCC2_DMAC_ID_MC_0 35
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#define TCC2_DMAC_ID_MC_1 36
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#define TCC2_DMAC_ID_MC_2 37
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#define TCC2_DMAC_ID_MC_LSB 35
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#define TCC2_DMAC_ID_MC_MSB 37
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#define TCC2_DMAC_ID_MC_SIZE 3
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#define TCC2_DMAC_ID_OVF 34 // DMA overflow/underflow/retrigger trigger
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#define TCC2_DTI 0 // Dead-Time-Insertion feature implemented
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#define TCC2_EXT 1 // Coding of implemented extended features
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#define TCC2_GCLK_ID 29 // Index of Generic Clock
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#define TCC2_MASTER_SLAVE_MODE 0 // TCC type 0 : NA, 1 : Master, 2 : Slave
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#define TCC2_OTMX 1 // Output Matrix feature implemented
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#define TCC2_OW_NUM 3 // Number of Output Waveforms
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#define TCC2_PG 0 // Pattern Generation feature implemented
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#define TCC2_SIZE 16
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#define TCC2_SWAP 0 // DTI outputs swap feature implemented
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#endif /* _SAMD51_TCC2_INSTANCE_ */
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