6839fff313
* atmel-samd: Remove ASF3. This will break builds. * atmel-samd: Add ASF4 for the SAMD21 and SAMD51. * Introduce the supervisor concept to facilitate porting. The supervisor is the code which runs individual MicroPython VMs. By splitting it out we make it more consistent and easier to find. This also adds very basic SAMD21 and SAMD51 support using the supervisor. Only the REPL currently works. This begins the work for #178.
54 lines
2.4 KiB
C
54 lines
2.4 KiB
C
/**
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* \file
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*
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* \brief Instance description for RAMECC
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*
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* Copyright (c) 2017 Atmel Corporation,
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* a wholly owned subsidiary of Microchip Technology Inc.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the Licence at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* \asf_license_stop
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*
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*/
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#ifndef _SAMD51_RAMECC_INSTANCE_
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#define _SAMD51_RAMECC_INSTANCE_
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/* ========== Register definition for RAMECC peripheral ========== */
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#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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#define REG_RAMECC_INTENCLR (0x41020000) /**< \brief (RAMECC) Interrupt Enable Clear */
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#define REG_RAMECC_INTENSET (0x41020001) /**< \brief (RAMECC) Interrupt Enable Set */
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#define REG_RAMECC_INTFLAG (0x41020002) /**< \brief (RAMECC) Interrupt Flag */
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#define REG_RAMECC_STATUS (0x41020003) /**< \brief (RAMECC) Status */
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#define REG_RAMECC_ERRADDR (0x41020004) /**< \brief (RAMECC) Error Address */
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#define REG_RAMECC_DBGCTRL (0x4102000F) /**< \brief (RAMECC) Debug Control */
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#else
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#define REG_RAMECC_INTENCLR (*(RwReg8 *)0x41020000UL) /**< \brief (RAMECC) Interrupt Enable Clear */
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#define REG_RAMECC_INTENSET (*(RwReg8 *)0x41020001UL) /**< \brief (RAMECC) Interrupt Enable Set */
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#define REG_RAMECC_INTFLAG (*(RwReg8 *)0x41020002UL) /**< \brief (RAMECC) Interrupt Flag */
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#define REG_RAMECC_STATUS (*(RoReg8 *)0x41020003UL) /**< \brief (RAMECC) Status */
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#define REG_RAMECC_ERRADDR (*(RoReg *)0x41020004UL) /**< \brief (RAMECC) Error Address */
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#define REG_RAMECC_DBGCTRL (*(RwReg8 *)0x4102000FUL) /**< \brief (RAMECC) Debug Control */
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#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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/* ========== Instance parameters for RAMECC peripheral ========== */
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#define RAMECC_RAMADDR_BITS 13 // Number of RAM address bits
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#define RAMECC_RAMBANK_NUM 4 // Number of RAM banks
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#endif /* _SAMD51_RAMECC_INSTANCE_ */
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