a9a219d8bf
It should be that: - duty_u16=0: output low, no pulse - duty_u16=65536: output high, no pulse That previously did not apply to all of the three PWM mechanisms of this port. This commit fixes it. Signed-off-by: robert-hh <robert@hammelrath.com>
44 lines
1.6 KiB
C
44 lines
1.6 KiB
C
/*
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* This file is part of the MicroPython project, http://micropython.org/
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*
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* Copyright (c) 2015, Freescale Semiconductor, Inc.
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* Copyright 2016-2017 NXP *
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* Copyright (c) 2021 Robert Hammelrath
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* SPDX-License-Identifier: BSD-3-Clause
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*
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*/
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#ifndef PWM_BACKPORT_H
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#define PWM_BACKPORT_H
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#include "fsl_pwm.h"
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#ifdef FSL_FEATURE_SOC_TMR_COUNT
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#include "fsl_qtmr.h"
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#endif
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typedef struct _pwm_signal_param_u16
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{
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pwm_channels_t pwmChannel; // PWM channel being configured; PWM A or PWM B
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uint32_t dutyCycle_u16; // PWM pulse width, value should be between 0 to 65536
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uint16_t Center_u16; // Center of the pulse, value should be between 0 to 65536
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pwm_level_select_t level; // PWM output active level select */
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uint16_t deadtimeValue; // The deadtime value; only used if channel pair is operating in complementary mode
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} pwm_signal_param_u16_t;
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#define PWM_FULL_SCALE (65536UL)
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void PWM_UpdatePwmDutycycle_u16(PWM_Type *base, pwm_submodule_t subModule,
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pwm_channels_t pwmSignal, uint32_t dutyCycle, uint16_t center);
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void PWM_SetupPwm_u16(PWM_Type *base, pwm_submodule_t subModule, pwm_signal_param_u16_t *chnlParams,
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uint32_t pwmFreq_Hz, uint32_t srcClock_Hz, bool output_enable);
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void PWM_SetupPwmx_u16(PWM_Type *base, pwm_submodule_t subModule,
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uint32_t pwmFreq_Hz, uint32_t duty_cycle, uint8_t invert, uint32_t srcClock_Hz);
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#ifdef FSL_FEATURE_SOC_TMR_COUNT
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status_t QTMR_SetupPwm_u16(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t pwmFreqHz,
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uint32_t dutyCycleU16, bool outputPolarity, uint32_t srcClock_Hz, bool is_init);
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#endif // FSL_FEATURE_SOC_TMR_COUNT
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#endif // PWM_BACKPORT_H
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