dd38d90724
This compiles and links, but hasn't been tested on a board yet and even if it was run, it doesn't currently do anything.
825 lines
24 KiB
C
825 lines
24 KiB
C
/**
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******************************************************************************
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* @file stm32f4xx_hal_sdram.c
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* @author MCD Application Team
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* @version V1.0.0
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* @date 18-February-2014
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* @brief SDRAM HAL module driver.
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* This file provides a generic firmware to drive SDRAM memories mounted
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* as external device.
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*
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@verbatim
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==============================================================================
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##### How to use this driver #####
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==============================================================================
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[..]
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This driver is a generic layered driver which contains a set of APIs used to
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control SDRAM memories. It uses the FMC layer functions to interface
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with SDRAM devices.
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The following sequence should be followed to configure the FMC to interface
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with SDRAM memories:
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(#) Declare a SDRAM_HandleTypeDef handle structure, for example:
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SDRAM_HandleTypeDef hdsram; and:
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(++) Fill the SDRAM_HandleTypeDef handle "Init" field with the allowed
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values of the structure member.
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(++) Fill the SDRAM_HandleTypeDef handle "Instance" field with a predefined
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base register instance for NOR or SDRAM device
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(#) Declare a FMC_SDRAM_TimingTypeDef structure; for example:
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FMC_SDRAM_TimingTypeDef Timing;
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and fill its fields with the allowed values of the structure member.
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(#) Initialize the SDRAM Controller by calling the function HAL_SDRAM_Init(). This function
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performs the following sequence:
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(##) MSP hardware layer configuration using the function HAL_SDRAM_MspInit()
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(##) Control register configuration using the FMC SDRAM interface function
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FMC_SDRAM_Init()
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(##) Timing register configuration using the FMC SDRAM interface function
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FMC_SDRAM_Timing_Init()
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(##) Program the SDRAM external device by applying its initialization sequence
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according to the device plugged in your hardware. This step is mandatory
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for accessing the SDRAM device.
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(#) At this stage you can perform read/write accesses from/to the memory connected
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to the SDRAM Bank. You can perform either polling or DMA transfer using the
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following APIs:
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(++) HAL_SDRAM_Read()/HAL_SDRAM_Write() for polling read/write access
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(++) HAL_SDRAM_Read_DMA()/HAL_SDRAM_Write_DMA() for DMA read/write transfer
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(#) You can also control the SDRAM device by calling the control APIs HAL_SDRAM_WriteOperation_Enable()/
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HAL_SDRAM_WriteOperation_Disable() to respectively enable/disable the SDRAM write operation or
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the function HAL_SDRAM_SendCommand() to send a specified command to the SDRAM
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device. The command to be sent must be configured with the FMC_SDRAM_CommandTypeDef
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structure.
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(#) You can continuously monitor the SDRAM device HAL state by calling the function
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HAL_SDRAM_GetState()
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@endverbatim
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of STMicroelectronics nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************
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*/
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/* Includes ------------------------------------------------------------------*/
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#include "stm32f4xx_hal.h"
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/** @addtogroup STM32F4xx_HAL_Driver
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* @{
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*/
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/** @defgroup SDRAM
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* @brief SDRAM driver modules
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* @{
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*/
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#ifdef HAL_SDRAM_MODULE_ENABLED
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#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
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/* Private typedef -----------------------------------------------------------*/
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/* Private define ------------------------------------------------------------*/
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/* Private macro -------------------------------------------------------------*/
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/* Private variables ---------------------------------------------------------*/
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/* Private function prototypes -----------------------------------------------*/
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/* Private functions ---------------------------------------------------------*/
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/** @defgroup SDRAM_Private_Functions
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* @{
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*/
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/** @defgroup SDRAM_Group1 Initialization and de-initialization functions
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* @brief Initialization and Configuration functions
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*
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@verbatim
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==============================================================================
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##### SDRAM Initialization and de_initialization functions #####
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==============================================================================
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[..]
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This section provides functions allowing to initialize/de-initialize
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the SDRAM memory
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@endverbatim
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* @{
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*/
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/**
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* @brief Performs the SDRAM device initialization sequence.
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* @param hsdram: SDRAM handle
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* @param Timing: Pointer to SDRAM control timing structure
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* @retval HAL status
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*/
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HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing)
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{
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/* Check the SDRAM handle parameter */
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if(hsdram == NULL)
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{
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return HAL_ERROR;
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}
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if(hsdram->State == HAL_SDRAM_STATE_RESET)
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{
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/* Initialize the low level hardware (MSP) */
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HAL_SDRAM_MspInit(hsdram);
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}
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/* Initialize the SDRAM controller state */
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hsdram->State = HAL_SDRAM_STATE_BUSY;
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/* Initialize SDRAM control Interface */
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FMC_SDRAM_Init(hsdram->Instance, &(hsdram->Init));
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/* Initialize SDRAM timing Interface */
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FMC_SDRAM_Timing_Init(hsdram->Instance, Timing, hsdram->Init.SDBank);
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/* Update the SDRAM controller state */
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hsdram->State = HAL_SDRAM_STATE_READY;
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return HAL_OK;
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}
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/**
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* @brief Perform the SDRAM device initialization sequence.
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* @param hsdram: SDRAM handle
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* @retval HAL status
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*/
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HAL_StatusTypeDef HAL_SDRAM_DeInit(SDRAM_HandleTypeDef *hsdram)
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{
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/* Initialize the low level hardware (MSP) */
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HAL_SDRAM_MspDeInit(hsdram);
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/* Configure the SDRAM registers with their reset values */
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FMC_SDRAM_DeInit(hsdram->Instance, hsdram->Init.SDBank);
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/* Reset the SDRAM controller state */
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hsdram->State = HAL_SDRAM_STATE_RESET;
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/* Release Lock */
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__HAL_UNLOCK(hsdram);
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return HAL_OK;
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}
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/**
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* @brief SDRAM MSP Init.
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* @param hsdram: SDRAM handle
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* @retval None
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*/
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__weak void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram)
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{
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/* NOTE: This function Should not be modified, when the callback is needed,
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the HAL_SDRAM_MspInit could be implemented in the user file
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*/
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}
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/**
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* @brief SDRAM MSP DeInit.
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* @param hsdram: SDRAM handle
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* @retval None
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*/
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__weak void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram)
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{
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/* NOTE: This function Should not be modified, when the callback is needed,
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the HAL_SDRAM_MspDeInit could be implemented in the user file
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*/
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}
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/**
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* @brief This function handles SDRAM refresh error interrupt request.
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* @param hsdram: SDRAM handle
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* @retval HAL status
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*/
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void HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef *hsdram)
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{
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/* Check SDRAM interrupt Rising edge flag */
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if(__FMC_SDRAM_GET_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_IT))
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{
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/* SDRAM refresh error interrupt callback */
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HAL_SDRAM_RefreshErrorCallback(hsdram);
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/* Clear SDRAM refresh error interrupt pending bit */
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__FMC_SDRAM_CLEAR_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_ERROR);
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}
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}
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/**
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* @brief SDRAM Refresh error callback.
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* @param hsdram: SDRAM handle
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* @retval None
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*/
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__weak void HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef *hsdram)
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{
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/* NOTE: This function Should not be modified, when the callback is needed,
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the HAL_SDRAM_RefreshErrorCallback could be implemented in the user file
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*/
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}
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/**
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* @brief DMA transfer complete callback.
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* @param hdma: DMA handle
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* @retval None
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*/
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__weak void HAL_SDRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma)
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{
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/* NOTE: This function Should not be modified, when the callback is needed,
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the HAL_SDRAM_DMA_XferCpltCallback could be implemented in the user file
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*/
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}
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/**
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* @brief DMA transfer complete error callback.
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* @param hdma: DMA handle
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* @retval None
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*/
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__weak void HAL_SDRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)
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{
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/* NOTE: This function Should not be modified, when the callback is needed,
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the HAL_SDRAM_DMA_XferErrorCallback could be implemented in the user file
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*/
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}
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/**
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* @}
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*/
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/** @defgroup SDRAM_Group2 Input and Output functions
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* @brief Input Output and memory control functions
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*
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@verbatim
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==============================================================================
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##### SDRAM Input and Output functions #####
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==============================================================================
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[..]
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This section provides functions allowing to use and control the SDRAM memory
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@endverbatim
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* @{
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*/
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/**
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* @brief Reads 8-bit data buffer from the SDRAM memory.
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* @param hsdram: SDRAM handle
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* @param pAddress: Pointer to read start address
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* @param pDstBuffer: Pointer to destination buffer
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* @param BufferSize: Size of the buffer to read from memory
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* @retval HAL status
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*/
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HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)
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{
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__IO uint8_t *pSdramAddress = (uint8_t *)pAddress;
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/* Process Locked */
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__HAL_LOCK(hsdram);
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/* Check the SDRAM controller state */
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if(hsdram->State == HAL_SDRAM_STATE_BUSY)
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{
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return HAL_BUSY;
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}
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else if(hsdram->State == HAL_SDRAM_STATE_PRECHARGED)
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{
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return HAL_ERROR;
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}
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/* Read data from source */
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for(; BufferSize != 0; BufferSize--)
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{
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*pDstBuffer = *(__IO uint8_t *)pSdramAddress;
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pDstBuffer++;
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pSdramAddress++;
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}
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/* Process Unlocked */
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__HAL_UNLOCK(hsdram);
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return HAL_OK;
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}
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/**
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* @brief Writes 8-bit data buffer to SDRAM memory.
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* @param hsdram: SDRAM handle
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* @param pAddress: Pointer to write start address
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* @param pSrcBuffer: Pointer to source buffer to write
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* @param BufferSize: Size of the buffer to write to memory
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* @retval HAL status
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*/
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HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)
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{
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__IO uint8_t *pSdramAddress = (uint8_t *)pAddress;
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uint32_t tmp = 0;
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/* Process Locked */
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__HAL_LOCK(hsdram);
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/* Check the SDRAM controller state */
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tmp = hsdram->State;
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if(tmp == HAL_SDRAM_STATE_BUSY)
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{
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return HAL_BUSY;
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}
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else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED))
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{
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return HAL_ERROR;
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}
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/* Write data to memory */
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for(; BufferSize != 0; BufferSize--)
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{
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*(__IO uint8_t *)pSdramAddress = *pSrcBuffer;
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pSrcBuffer++;
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pSdramAddress++;
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}
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/* Process Unlocked */
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__HAL_UNLOCK(hsdram);
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return HAL_OK;
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}
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/**
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* @brief Reads 16-bit data buffer from the SDRAM memory.
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* @param hsdram: SDRAM handle
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* @param pAddress: Pointer to read start address
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* @param pDstBuffer: Pointer to destination buffer
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* @param BufferSize: Size of the buffer to read from memory
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* @retval HAL status
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*/
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HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)
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{
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__IO uint16_t *pSdramAddress = (uint16_t *)pAddress;
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/* Process Locked */
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__HAL_LOCK(hsdram);
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/* Check the SDRAM controller state */
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if(hsdram->State == HAL_SDRAM_STATE_BUSY)
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{
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return HAL_BUSY;
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}
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else if(hsdram->State == HAL_SDRAM_STATE_PRECHARGED)
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{
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return HAL_ERROR;
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}
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/* Read data from source */
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for(; BufferSize != 0; BufferSize--)
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{
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*pDstBuffer = *(__IO uint16_t *)pSdramAddress;
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pDstBuffer++;
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pSdramAddress++;
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}
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/* Process Unlocked */
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__HAL_UNLOCK(hsdram);
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return HAL_OK;
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}
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/**
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* @brief Writes 16-bit data buffer to SDRAM memory.
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* @param hsdram: SDRAM handle
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* @param pAddress: Pointer to write start address
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* @param pSrcBuffer: Pointer to source buffer to write
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* @param BufferSize: Size of the buffer to write to memory
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* @retval HAL status
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*/
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HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)
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{
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__IO uint16_t *pSdramAddress = (uint16_t *)pAddress;
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uint32_t tmp = 0;
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/* Process Locked */
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__HAL_LOCK(hsdram);
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/* Check the SDRAM controller state */
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tmp = hsdram->State;
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if(tmp == HAL_SDRAM_STATE_BUSY)
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{
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return HAL_BUSY;
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}
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else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED))
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{
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return HAL_ERROR;
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}
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/* Write data to memory */
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for(; BufferSize != 0; BufferSize--)
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{
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*(__IO uint16_t *)pSdramAddress = *pSrcBuffer;
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pSrcBuffer++;
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pSdramAddress++;
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}
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/* Process Unlocked */
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__HAL_UNLOCK(hsdram);
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return HAL_OK;
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}
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/**
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* @brief Reads 32-bit data buffer from the SDRAM memory.
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* @param hsdram: SDRAM handle
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* @param pAddress: Pointer to read start address
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* @param pDstBuffer: Pointer to destination buffer
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* @param BufferSize: Size of the buffer to read from memory
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* @retval HAL status
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*/
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HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
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{
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__IO uint32_t *pSdramAddress = (uint32_t *)pAddress;
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/* Process Locked */
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__HAL_LOCK(hsdram);
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/* Check the SDRAM controller state */
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if(hsdram->State == HAL_SDRAM_STATE_BUSY)
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{
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return HAL_BUSY;
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}
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else if(hsdram->State == HAL_SDRAM_STATE_PRECHARGED)
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{
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return HAL_ERROR;
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}
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/* Read data from source */
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for(; BufferSize != 0; BufferSize--)
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{
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*pDstBuffer = *(__IO uint32_t *)pSdramAddress;
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pDstBuffer++;
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pSdramAddress++;
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}
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/* Process Unlocked */
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__HAL_UNLOCK(hsdram);
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return HAL_OK;
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}
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/**
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* @brief Writes 32-bit data buffer to SDRAM memory.
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* @param hsdram: SDRAM handle
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* @param pAddress: Pointer to write start address
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* @param pSrcBuffer: Pointer to source buffer to write
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* @param BufferSize: Size of the buffer to write to memory
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* @retval HAL status
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*/
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HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
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{
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__IO uint32_t *pSdramAddress = (uint32_t *)pAddress;
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uint32_t tmp = 0;
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/* Process Locked */
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__HAL_LOCK(hsdram);
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/* Check the SDRAM controller state */
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tmp = hsdram->State;
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if(tmp == HAL_SDRAM_STATE_BUSY)
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{
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return HAL_BUSY;
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}
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else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED))
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{
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return HAL_ERROR;
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}
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/* Write data to memory */
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for(; BufferSize != 0; BufferSize--)
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{
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*(__IO uint32_t *)pSdramAddress = *pSrcBuffer;
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pSrcBuffer++;
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pSdramAddress++;
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}
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/* Process Unlocked */
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__HAL_UNLOCK(hsdram);
|
|
|
|
return HAL_OK;
|
|
}
|
|
|
|
/**
|
|
* @brief Reads a Words data from the SDRAM memory using DMA transfer.
|
|
* @param hsdram: SDRAM handle
|
|
* @param pAddress: Pointer to read start address
|
|
* @param pDstBuffer: Pointer to destination buffer
|
|
* @param BufferSize: Size of the buffer to read from memory
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
|
|
{
|
|
uint32_t tmp = 0;
|
|
|
|
/* Process Locked */
|
|
__HAL_LOCK(hsdram);
|
|
|
|
/* Check the SDRAM controller state */
|
|
tmp = hsdram->State;
|
|
|
|
if(tmp == HAL_SDRAM_STATE_BUSY)
|
|
{
|
|
return HAL_BUSY;
|
|
}
|
|
else if(tmp == HAL_SDRAM_STATE_PRECHARGED)
|
|
{
|
|
return HAL_ERROR;
|
|
}
|
|
|
|
/* Configure DMA user callbacks */
|
|
hsdram->hdma->XferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback;
|
|
hsdram->hdma->XferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback;
|
|
|
|
/* Enable the DMA Stream */
|
|
HAL_DMA_Start_IT(hsdram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize);
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hsdram);
|
|
|
|
return HAL_OK;
|
|
}
|
|
|
|
/**
|
|
* @brief Writes a Words data buffer to SDRAM memory using DMA transfer.
|
|
* @param hsdram: SDRAM handle
|
|
* @param pAddress: Pointer to write start address
|
|
* @param pSrcBuffer: Pointer to source buffer to write
|
|
* @param BufferSize: Size of the buffer to write to memory
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
|
|
{
|
|
uint32_t tmp = 0;
|
|
|
|
/* Process Locked */
|
|
__HAL_LOCK(hsdram);
|
|
|
|
/* Check the SDRAM controller state */
|
|
tmp = hsdram->State;
|
|
|
|
if(tmp == HAL_SDRAM_STATE_BUSY)
|
|
{
|
|
return HAL_BUSY;
|
|
}
|
|
else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED))
|
|
{
|
|
return HAL_ERROR;
|
|
}
|
|
|
|
/* Configure DMA user callbacks */
|
|
hsdram->hdma->XferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback;
|
|
hsdram->hdma->XferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback;
|
|
|
|
/* Enable the DMA Stream */
|
|
HAL_DMA_Start_IT(hsdram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize);
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hsdram);
|
|
|
|
return HAL_OK;
|
|
}
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup SDRAM_Group3 Control functions
|
|
* @brief management functions
|
|
*
|
|
@verbatim
|
|
==============================================================================
|
|
##### SDRAM Control functions #####
|
|
==============================================================================
|
|
[..]
|
|
This subsection provides a set of functions allowing to control dynamically
|
|
the SDRAM interface.
|
|
|
|
@endverbatim
|
|
* @{
|
|
*/
|
|
|
|
/**
|
|
* @brief Enables dynamically SDRAM write protection.
|
|
* @param hsdram: SDRAM handle
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Enable(SDRAM_HandleTypeDef *hsdram)
|
|
{
|
|
/* Check the SDRAM controller state */
|
|
if(hsdram->State == HAL_SDRAM_STATE_BUSY)
|
|
{
|
|
return HAL_BUSY;
|
|
}
|
|
|
|
/* Update the SDRAM state */
|
|
hsdram->State = HAL_SDRAM_STATE_BUSY;
|
|
|
|
/* Enable write protection */
|
|
FMC_SDRAM_WriteProtection_Enable(hsdram->Instance, hsdram->Init.SDBank);
|
|
|
|
/* Update the SDRAM state */
|
|
hsdram->State = HAL_SDRAM_STATE_WRITE_PROTECTED;
|
|
|
|
return HAL_OK;
|
|
}
|
|
|
|
/**
|
|
* @brief Disables dynamically SDRAM write protection.
|
|
* @param hsdram: SDRAM handle
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef *hsdram)
|
|
{
|
|
/* Check the SDRAM controller state */
|
|
if(hsdram->State == HAL_SDRAM_STATE_BUSY)
|
|
{
|
|
return HAL_BUSY;
|
|
}
|
|
|
|
/* Update the SDRAM state */
|
|
hsdram->State = HAL_SDRAM_STATE_BUSY;
|
|
|
|
/* Disable write protection */
|
|
FMC_SDRAM_WriteProtection_Disable(hsdram->Instance, hsdram->Init.SDBank);
|
|
|
|
/* Update the SDRAM state */
|
|
hsdram->State = HAL_SDRAM_STATE_READY;
|
|
|
|
return HAL_OK;
|
|
}
|
|
|
|
/**
|
|
* @brief Sends Command to the SDRAM bank.
|
|
* @param hsdram: SDRAM handle
|
|
* @param Command: SDRAM command structure
|
|
* @param Timeout: Timeout duration
|
|
* @retval HAL state
|
|
*/
|
|
HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout)
|
|
{
|
|
/* Check the SDRAM controller state */
|
|
if(hsdram->State == HAL_SDRAM_STATE_BUSY)
|
|
{
|
|
return HAL_BUSY;
|
|
}
|
|
|
|
/* Update the SDRAM state */
|
|
hsdram->State = HAL_SDRAM_STATE_BUSY;
|
|
|
|
/* Send SDRAM command */
|
|
FMC_SDRAM_SendCommand(hsdram->Instance, Command, Timeout);
|
|
|
|
/* Update the SDRAM controller state state */
|
|
if(Command->CommandMode == FMC_SDRAM_CMD_PALL)
|
|
{
|
|
hsdram->State = HAL_SDRAM_STATE_PRECHARGED;
|
|
}
|
|
else
|
|
{
|
|
hsdram->State = HAL_SDRAM_STATE_READY;
|
|
}
|
|
|
|
return HAL_OK;
|
|
}
|
|
|
|
/**
|
|
* @brief Programs the SDRAM Memory Refresh rate.
|
|
* @param hsdram: SDRAM handle
|
|
* @param RefreshRate: The SDRAM refresh rate value
|
|
* @retval HAL state
|
|
*/
|
|
HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate)
|
|
{
|
|
/* Check the SDRAM controller state */
|
|
if(hsdram->State == HAL_SDRAM_STATE_BUSY)
|
|
{
|
|
return HAL_BUSY;
|
|
}
|
|
|
|
/* Update the SDRAM state */
|
|
hsdram->State = HAL_SDRAM_STATE_BUSY;
|
|
|
|
/* Program the refresh rate */
|
|
FMC_SDRAM_ProgramRefreshRate(hsdram->Instance ,RefreshRate);
|
|
|
|
/* Update the SDRAM state */
|
|
hsdram->State = HAL_SDRAM_STATE_READY;
|
|
|
|
return HAL_OK;
|
|
}
|
|
|
|
/**
|
|
* @brief Sets the Number of consecutive SDRAM Memory auto Refresh commands.
|
|
* @param hsdram: SDRAM handle
|
|
* @param AutoRefreshNumber: The SDRAM auto Refresh number
|
|
* @retval None
|
|
*/
|
|
HAL_StatusTypeDef HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef *hsdram, uint32_t AutoRefreshNumber)
|
|
{
|
|
/* Check the SDRAM controller state */
|
|
if(hsdram->State == HAL_SDRAM_STATE_BUSY)
|
|
{
|
|
return HAL_BUSY;
|
|
}
|
|
|
|
/* Update the SDRAM state */
|
|
hsdram->State = HAL_SDRAM_STATE_BUSY;
|
|
|
|
/* Set the Auto-Refresh number */
|
|
FMC_SDRAM_SetAutoRefreshNumber(hsdram->Instance ,AutoRefreshNumber);
|
|
|
|
/* Update the SDRAM state */
|
|
hsdram->State = HAL_SDRAM_STATE_READY;
|
|
|
|
return HAL_OK;
|
|
}
|
|
|
|
/**
|
|
* @brief Returns the SDRAM memory current mode.
|
|
* @param hsdram: SDRAM handle
|
|
* @retval The SDRAM memory mode.
|
|
*/
|
|
uint32_t HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram)
|
|
{
|
|
/* Return the SDRAM memory current mode */
|
|
return(FMC_SDRAM_GetModeStatus(hsdram->Instance, hsdram->Init.SDBank));
|
|
}
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup SDRAM_Group4 State functions
|
|
* @brief Peripheral State functions
|
|
*
|
|
@verbatim
|
|
==============================================================================
|
|
##### SDRAM State functions #####
|
|
==============================================================================
|
|
[..]
|
|
This subsection permits to get in run-time the status of the SDRAM controller
|
|
and the data flow.
|
|
|
|
@endverbatim
|
|
* @{
|
|
*/
|
|
|
|
/**
|
|
* @brief Returns the SDRAM state.
|
|
* @param hsdram: SDRAM handle
|
|
* @retval HAL state
|
|
*/
|
|
HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram)
|
|
{
|
|
return hsdram->State;
|
|
}
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
|
|
#endif /* HAL_SDRAM_MODULE_ENABLED */
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|