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circuitpython/ports/stm32/boards/B_L072Z_LRWAN1
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Angus Gratton 4548928449 stm32/boards/B_L072Z_LRWAN1: Lower default ROM level to "Core". 
Re-enable some features required for the board to still build and the lora
driver to run.

This board only has 192KB of flash total, so default stm32 build is very
close to the limit.

Before:

LINK build-B_L072Z_LRWAN1/firmware.elf
   text    data     bss     dec     hex filename
 184352      68   14112  198532   30784 build-B_L072Z_LRWAN1/firmware.elf

(12256 bytes free)

After:

LINK build-B_L072Z_LRWAN1/firmware.elf
   text    data     bss     dec     hex filename
 155028      68   14052  169148   294bc build-B_L072Z_LRWAN1/firmware.elf

(41580 bytes free)

This work was funded through GitHub Sponsors.

Signed-off-by: Angus Gratton <angus@redyak.com.au>
2023-07-20 21:48:10 +10:00
..
board.json ports: Update board.json files to link to new board images. 2022-01-07 11:33:28 +11:00
mpconfigboard.h stm32/boards/B_L072Z_LRWAN1: Lower default ROM level to "Core". 2023-07-20 21:48:10 +10:00
mpconfigboard.mk stm32/boards: Enable LTO by default on boards with smaller flash size. 2022-06-28 10:32:39 +10:00
pins.csv stm32/boards/B_L072Z_LRWAN1: Add pin definitions for internal SX1262. 2023-07-20 21:47:55 +10:00
stm32l0xx_hal_conf.h stm32/boards/B_L072Z_LRWAN1: Add definition files for new board. 2019-07-09 12:54:09 +10:00