1074c784b0
Hyperflash is used by the MIMXRT1050_EVKB, MIMXRT1060_EVK and MIMXRT1064_EVK boards. This commit includes: - add support for Hyperflash - modify MIMXRT1060_EVK and MIMXRT1064_EVK to change from QSPI to hyperflash. - minor incidental changes to other boards so they still build Note: Erasing a sector on the hyperflash is slow. It takes about a second, which seems too long, but matches the data sheet.
67 lines
2.7 KiB
C
67 lines
2.7 KiB
C
#define MICROPY_HW_BOARD_NAME "i.MX RT1020 EVK"
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#define MICROPY_HW_MCU_NAME "MIMXRT1021DAG5A"
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#define BOARD_FLASH_SIZE (8 * 1024 * 1024)
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// i.MX RT1020 EVK has 1 board LED
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// Todo: think about replacing the define with searching in the generated pins?
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#define MICROPY_HW_LED1_PIN (pin_GPIO_AD_B0_05)
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#define MICROPY_HW_LED_ON(pin) (mp_hal_pin_low(pin))
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#define MICROPY_HW_LED_OFF(pin) (mp_hal_pin_high(pin))
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#define BOARD_FLASH_CONFIG_HEADER_H "evkmimxrt1020_flexspi_nor_config.h"
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#define BOARD_FLASH_OPS_HEADER_H "hal/flexspi_nor_flash.h"
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#define MICROPY_HW_NUM_PIN_IRQS (3 * 32)
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// Define mapping logical UART # to hardware UART #
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// RX/TX HW-UART Logical UART
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// D3/D5 LPUART1 Not usable, Since D3 is blocked.
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// D0/D1 LPUART2 -> 1
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// D6/D9 LPUART3 -> 2
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// D10/D12 LPUART5 -> 3
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// D14/D15 LPUART8 -> 4
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// A0/A1 LPUART4 -> 5
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#define MICROPY_HW_UART_NUM (sizeof(uart_index_table) / sizeof(uart_index_table)[0])
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#define MICROPY_HW_UART_INDEX { 0, 2, 3, 5, 8, 4 }
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#define IOMUX_TABLE_UART \
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{ IOMUXC_GPIO_AD_B0_06_LPUART1_TX }, { IOMUXC_GPIO_AD_B0_07_LPUART1_RX }, \
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{ IOMUXC_GPIO_AD_B1_08_LPUART2_TX }, { IOMUXC_GPIO_AD_B1_09_LPUART2_RX }, \
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{ IOMUXC_GPIO_AD_B0_14_LPUART3_TX }, { IOMUXC_GPIO_AD_B0_15_LPUART3_RX }, \
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{ IOMUXC_GPIO_AD_B1_10_LPUART4_TX }, { IOMUXC_GPIO_AD_B1_11_LPUART4_RX }, \
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{ IOMUXC_GPIO_AD_B0_10_LPUART5_TX }, { IOMUXC_GPIO_AD_B0_11_LPUART5_RX }, \
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{ 0 }, { 0 }, \
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{ 0 }, { 0 }, \
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{ IOMUXC_GPIO_SD_B1_02_LPUART8_TX }, { IOMUXC_GPIO_SD_B1_03_LPUART8_RX },
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#define MICROPY_HW_SPI_INDEX { 1, 3 }
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#define IOMUX_TABLE_SPI \
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{ IOMUXC_GPIO_AD_B0_10_LPSPI1_SCK }, { IOMUXC_GPIO_AD_B0_11_LPSPI1_PCS0 }, \
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{ IOMUXC_GPIO_AD_B0_12_LPSPI1_SDO }, { IOMUXC_GPIO_AD_B0_13_LPSPI1_SDI }, \
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{ 0 }, { 0 }, \
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{ 0 }, { 0 }, \
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{ IOMUXC_GPIO_AD_B1_12_LPSPI3_SCK }, { IOMUXC_GPIO_AD_B1_13_LPSPI3_PCS0 }, \
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{ IOMUXC_GPIO_AD_B1_14_LPSPI3_SDO }, { IOMUXC_GPIO_AD_B1_15_LPSPI3_SDI },
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#define DMA_REQ_SRC_RX { 0, kDmaRequestMuxLPSPI1Rx, kDmaRequestMuxLPSPI2Rx, \
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kDmaRequestMuxLPSPI3Rx, kDmaRequestMuxLPSPI4Rx }
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#define DMA_REQ_SRC_TX { 0, kDmaRequestMuxLPSPI1Tx, kDmaRequestMuxLPSPI2Tx, \
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kDmaRequestMuxLPSPI3Tx, kDmaRequestMuxLPSPI4Tx }
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// Define mapping hardware I2C # to logical I2C #
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// SDA/SCL HW-I2C Logical I2C
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// D14/D15 LPI2C4 -> 0
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// A4/A5 LPI2C1 -> 1
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// D0/D1 LPI2C2 -> 2
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#define MICROPY_HW_I2C_INDEX { 4, 1, 2 }
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#define IOMUX_TABLE_I2C \
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{ IOMUXC_GPIO_AD_B1_14_LPI2C1_SCL }, { IOMUXC_GPIO_AD_B1_15_LPI2C1_SDA }, \
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{ IOMUXC_GPIO_AD_B1_08_LPI2C2_SCL }, { IOMUXC_GPIO_AD_B1_09_LPI2C2_SDA }, \
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{ 0 }, { 0 }, \
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{ IOMUXC_GPIO_SD_B1_02_LPI2C4_SCL }, { IOMUXC_GPIO_SD_B1_03_LPI2C4_SDA },
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