137 lines
6.3 KiB
C
137 lines
6.3 KiB
C
/*
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* This file is part of the MicroPython project, http://micropython.org/
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2020 microDev
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* Copyright (c) 2023 Bob Abeles
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include <string.h>
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#include "shared-bindings/memorymap/AddressRange.h"
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#include "py/runtime.h"
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#include "hardware/regs/addressmap.h"
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// RP2 address map ranges, must be arranged in order by ascending start address
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addressmap_rp2_range_t rp2_ranges[] = {
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{(uint8_t *)ROM_BASE, 0x00004000, ROM}, // boot ROM
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{(uint8_t *)XIP_BASE, 0x00100000, XIP}, // XIP normal cache operation
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{(uint8_t *)XIP_NOALLOC_BASE, 0x00100000, XIP}, // XIP check for hit, no update on miss
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{(uint8_t *)XIP_NOCACHE_BASE, 0x00100000, XIP}, // XIP don't check for hit, no update on miss
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{(uint8_t *)XIP_NOCACHE_NOALLOC_BASE, 0x00100000, XIP}, // XIP bypass cache completely
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{(uint8_t *)XIP_CTRL_BASE, 0x00004000, IO}, // XIP control registers
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{(uint8_t *)XIP_SRAM_BASE, 0x00004000, SRAM}, // XIP SRAM 16KB XIP cache
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{(uint8_t *)XIP_SSI_BASE, 0x00004000, IO}, // XIP SSI registers
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{(uint8_t *)SRAM_BASE, 0x00042000, SRAM}, // SRAM 256KB striped plus 16KB contiguous
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{(uint8_t *)SRAM0_BASE, 0x00040000, SRAM}, // SRAM0 to SRAM3 256KB non-striped
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{(uint8_t *)SYSINFO_BASE, 0x00070000, IO}, // APB peripherals
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{(uint8_t *)DMA_BASE, 0x00004000, IO}, // DMA registers
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{(uint8_t *)USBCTRL_DPRAM_BASE, 0x00001000, SRAM}, // USB DPSRAM 4KB
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{(uint8_t *)USBCTRL_REGS_BASE, 0x00004000, IO}, // USB registers
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{(uint8_t *)PIO0_BASE, 0x00004000, IO}, // PIO0 registers
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{(uint8_t *)PIO1_BASE, 0x00004000, IO}, // PIO1 registers
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{(uint8_t *)SIO_BASE, 0x00001000, IO}, // SIO registers, no aliases
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{(uint8_t *)PPB_BASE, 0x00004000, IO} // PPB registers
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};
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void common_hal_memorymap_addressrange_construct(memorymap_addressrange_obj_t *self,
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uint8_t *start_address, size_t length) {
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for (size_t i = 0; i < MP_ARRAY_SIZE(rp2_ranges); i++) {
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if (start_address <= rp2_ranges[i].start_address) {
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uint8_t *range_end_address = rp2_ranges[i].start_address + rp2_ranges[i].len - 1;
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uint8_t *end_address = start_address + length - 1;
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if (start_address > range_end_address || end_address > range_end_address) {
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break;
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}
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self->start_address = start_address;
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self->len = length;
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self->type = rp2_ranges[i].type;
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return;
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}
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}
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mp_raise_ValueError(translate("Address range not allowed"));
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}
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size_t common_hal_memorymap_addressrange_get_length(const memorymap_addressrange_obj_t *self) {
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return self->len;
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}
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void common_hal_memorymap_addressrange_set_bytes(const memorymap_addressrange_obj_t *self,
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size_t start_index, uint8_t *values, size_t len) {
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uint8_t *dest_addr = self->start_address + start_index;
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switch (self->type) {
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case SRAM:
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// Writes to SRAM may be arbitrary length and alignment. We use memcpy() which
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// may optimize aligned writes depending on CIRCUITPY_FULL_BUILD of the CP build.
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memcpy(dest_addr, values, len);
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break;
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case IO:
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if ((size_t)dest_addr & 0x03 || len & 0x03) {
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// Unaligned access or unaligned length not supported by RP2 for IO registers
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mp_raise_RuntimeError(translate("Unable to access unaligned IO register"));
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} else {
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// Aligned access and length, use 32-bit writes
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uint32_t *dest_addr32 = (uint32_t *)dest_addr;
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size_t access_count = len >> 2;
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for (size_t i = 0; i < access_count; i++) {
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*dest_addr32++ = ((uint32_t *)values)[i];
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}
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}
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break;
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case XIP:
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case ROM:
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// XIP and ROM are read-only
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mp_raise_RuntimeError(translate("Unable to write to read-only memory"));
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break;
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}
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}
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void common_hal_memorymap_addressrange_get_bytes(const memorymap_addressrange_obj_t *self,
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size_t start_index, size_t len, uint8_t *values) {
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uint8_t *src_addr = self->start_address + start_index;
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switch (self->type) {
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case SRAM:
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case XIP:
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case ROM:
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// Reads from these sources may be arbitrary length and alignment. We use memcpy()
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// which may optimize aligned writes depending on CIRCUITPY_FULL_BUILD of the CP build.
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memcpy(values, src_addr, len);
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break;
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case IO:
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if ((size_t)src_addr & 0x03 || len & 0x03) {
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// Unaligned access or unaligned length not supported by RP2 for IO registers
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mp_raise_RuntimeError(translate("Unable to access unaligned IO register"));
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} else {
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// Aligned access and length, use 32-bit reads
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uint32_t *src_addr32 = (uint32_t *)src_addr;
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size_t access_count = len >> 2;
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for (size_t i = 0; i < access_count; i++) {
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((uint32_t *)values)[i] = *src_addr32++;
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}
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}
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break;
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}
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}
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