iabdalkader 7649f5fbd2 stm32/sdram: Make SDRAM test cache aware, and optional failure with msg.
* Make SDRAM test cache-aware for newer MCUs.
* Use the defined data bus width (instead of the fixed 8-bits).
* Allow optional failure on error with verbose error messages.
* Test speed is now inverted (test accepts exhaustive instead fast).
2021-07-22 16:47:49 +10:00
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