426 lines
13 KiB
C
426 lines
13 KiB
C
/*
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* This file is part of the MicroPython project, http://micropython.org/
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2018 Scott Shawcroft for Adafruit Industries
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "clocks.h"
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#include "hpl_gclk_config.h"
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#include "bindings/samd/Clock.h"
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#include "shared-bindings/microcontroller/__init__.h"
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#include "py/runtime.h"
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bool gclk_enabled(uint8_t gclk) {
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common_hal_mcu_disable_interrupts();
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// Explicitly do a byte write so the peripheral knows we're just wanting to read the channel
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// rather than write to it.
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*((uint8_t*) &GCLK->GENCTRL.reg) = gclk;
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while (GCLK->STATUS.bit.SYNCBUSY == 1) {}
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bool enabled = GCLK->GENCTRL.bit.GENEN;
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common_hal_mcu_enable_interrupts();
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return enabled;
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}
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void disable_gclk(uint8_t gclk) {
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while (GCLK->STATUS.bit.SYNCBUSY == 1) {}
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GCLK->GENCTRL.reg = GCLK_GENCTRL_ID(gclk);
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while (GCLK->STATUS.bit.SYNCBUSY == 1) {}
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}
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void connect_gclk_to_peripheral(uint8_t gclk, uint8_t peripheral) {
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GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID(peripheral) | GCLK_CLKCTRL_GEN(gclk) | GCLK_CLKCTRL_CLKEN;
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}
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void disconnect_gclk_from_peripheral(uint8_t gclk, uint8_t peripheral) {
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GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID(peripheral) | GCLK_CLKCTRL_GEN(gclk);
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}
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void enable_clock_generator(uint8_t gclk, uint32_t source, uint16_t divisor) {
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uint32_t divsel = 0;
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if (gclk == 2 && divisor > 31) {
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divsel = GCLK_GENCTRL_DIVSEL;
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for (int i = 15; i > 4; i++) {
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if (divisor & (1 << i)) {
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divisor = i - 1;
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break;
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}
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}
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}
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GCLK->GENDIV.reg = GCLK_GENDIV_ID(gclk) | GCLK_GENDIV_DIV(divisor);
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GCLK->GENCTRL.reg = GCLK_GENCTRL_ID(gclk) | GCLK_GENCTRL_SRC(source) | divsel | GCLK_GENCTRL_OE | GCLK_GENCTRL_GENEN;
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while (GCLK->STATUS.bit.SYNCBUSY != 0) {}
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}
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void disable_clock_generator(uint8_t gclk) {
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GCLK->GENCTRL.reg = GCLK_GENCTRL_ID(gclk);
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while (GCLK->STATUS.bit.SYNCBUSY != 0) {}
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}
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static void init_clock_source_osc8m(void) {
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// Preserve CALIB and FRANGE
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SYSCTRL->OSC8M.bit.ONDEMAND = 0;
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SYSCTRL->OSC8M.bit.PRESC = 3;
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SYSCTRL->OSC8M.bit.ENABLE = 1;
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while (!SYSCTRL->PCLKSR.bit.OSC8MRDY) {}
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}
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static void init_clock_source_osc32k(void) {
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uint32_t calib = (*((uint32_t *)FUSES_OSC32K_CAL_ADDR) & FUSES_OSC32K_CAL_Msk) >> FUSES_OSC32K_CAL_Pos;
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SYSCTRL->OSC32K.reg = SYSCTRL_OSC32K_CALIB(calib) |
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SYSCTRL_OSC32K_EN32K |
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SYSCTRL_OSC32K_ENABLE;
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while (!SYSCTRL->PCLKSR.bit.OSC32KRDY) {}
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}
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static void init_clock_source_xosc32k(void) {
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SYSCTRL->XOSC32K.reg = SYSCTRL_XOSC32K_EN32K |
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SYSCTRL_XOSC32K_XTALEN |
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SYSCTRL_XOSC32K_ENABLE;
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while (!SYSCTRL->PCLKSR.bit.XOSC32KRDY) {}
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}
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static void init_clock_source_dfll48m(void) {
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SYSCTRL->DFLLCTRL.reg = SYSCTRL_DFLLCTRL_ENABLE;
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while (!SYSCTRL->PCLKSR.bit.DFLLRDY) {}
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SYSCTRL->DFLLMUL.reg = SYSCTRL_DFLLMUL_CSTEP(1) |
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SYSCTRL_DFLLMUL_FSTEP(1) |
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SYSCTRL_DFLLMUL_MUL(48000);
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uint32_t coarse = (*((uint32_t *)FUSES_DFLL48M_COARSE_CAL_ADDR) & FUSES_DFLL48M_COARSE_CAL_Msk) >> FUSES_DFLL48M_COARSE_CAL_Pos;
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if (coarse == 0x3f)
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coarse = 0x1f;
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SYSCTRL->DFLLVAL.reg = SYSCTRL_DFLLVAL_COARSE(coarse) |
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SYSCTRL_DFLLVAL_FINE(512);
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SYSCTRL->DFLLCTRL.reg = SYSCTRL_DFLLCTRL_CCDIS |
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SYSCTRL_DFLLCTRL_USBCRM |
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SYSCTRL_DFLLCTRL_MODE |
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SYSCTRL_DFLLCTRL_ENABLE;
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while (!SYSCTRL->PCLKSR.bit.DFLLRDY) {}
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while (GCLK->STATUS.bit.SYNCBUSY) {}
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}
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void clock_init(void)
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{
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init_clock_source_osc8m();
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if (board_has_crystal())
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init_clock_source_xosc32k();
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else
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init_clock_source_osc32k();
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enable_clock_generator(0, GCLK_GENCTRL_SRC_DFLL48M_Val, 1);
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enable_clock_generator(1, GCLK_GENCTRL_SRC_DFLL48M_Val, 150);
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init_clock_source_dfll48m();
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if (board_has_crystal())
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enable_clock_generator(2, GCLK_GENCTRL_SRC_XOSC32K_Val, 32);
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else
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enable_clock_generator(2, GCLK_GENCTRL_SRC_OSC32K_Val, 32);
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}
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static bool clk_enabled(uint8_t clk) {
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common_hal_mcu_disable_interrupts();
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*((uint8_t*) &GCLK->CLKCTRL.reg) = clk;
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while (GCLK->STATUS.bit.SYNCBUSY == 1) {}
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bool enabled = GCLK->CLKCTRL.bit.CLKEN;
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common_hal_mcu_enable_interrupts();
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return enabled;
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}
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static uint8_t clk_get_generator(uint8_t clk) {
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common_hal_mcu_disable_interrupts();
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*((uint8_t*) &GCLK->CLKCTRL.reg) = clk;
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while (GCLK->STATUS.bit.SYNCBUSY == 1) {}
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uint8_t gen = GCLK->CLKCTRL.bit.GEN;
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common_hal_mcu_enable_interrupts();
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return gen;
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}
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static uint8_t generator_get_source(uint8_t gen) {
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common_hal_mcu_disable_interrupts();
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*((uint8_t*) &GCLK->GENCTRL.reg) = gen;
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while (GCLK->STATUS.bit.SYNCBUSY == 1) {}
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uint8_t src = GCLK->GENCTRL.bit.SRC;
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common_hal_mcu_enable_interrupts();
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return src;
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}
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static bool osc_enabled(uint8_t index) {
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switch (index) {
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case GCLK_SOURCE_XOSC:
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return SYSCTRL->XOSC.bit.ENABLE;
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// TODO: GCLK_SOURCE_GCLKIN
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// TODO: GCLK_SOURCE_GCLKGEN1
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case GCLK_SOURCE_OSCULP32K:
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return true;
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case GCLK_SOURCE_OSC32K:
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return SYSCTRL->OSC32K.bit.ENABLE;
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case GCLK_SOURCE_XOSC32K:
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return SYSCTRL->XOSC32K.bit.ENABLE;
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case GCLK_SOURCE_OSC8M:
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return SYSCTRL->OSC8M.bit.ENABLE;
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case GCLK_SOURCE_DFLL48M:
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return SYSCTRL->DFLLCTRL.bit.ENABLE;
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case GCLK_SOURCE_DPLL96M:
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return SYSCTRL->DPLLCTRLA.bit.ENABLE;
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};
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return false;
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}
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static uint32_t osc_get_frequency(uint8_t index) {
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switch (index) {
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case GCLK_SOURCE_XOSC:
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return 0; // unknown 0.4-32MHz
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// TODO: GCLK_SOURCE_GCLKIN
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// TODO: GCLK_SOURCE_GCLKGEN1
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case GCLK_SOURCE_OSCULP32K:
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case GCLK_SOURCE_OSC32K:
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case GCLK_SOURCE_XOSC32K:
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return 32768;
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case GCLK_SOURCE_OSC8M:
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return 8000000;
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case GCLK_SOURCE_DFLL48M:
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return 48000000;
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case GCLK_SOURCE_DPLL96M:
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return 96000000;
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}
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return 0;
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}
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bool clock_get_enabled(uint8_t type, uint8_t index) {
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if (type == 0)
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return osc_enabled(index);
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if (type == 1)
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return clk_enabled(index);
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if (type == 2)
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return SysTick->CTRL & SysTick_CTRL_ENABLE_Msk;
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return false;
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}
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bool clock_get_parent(uint8_t type, uint8_t index, uint8_t *p_type, uint8_t *p_index) {
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if (type == 1 && index <= 0x24 && clk_enabled(index)) {
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*p_type = 0;
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*p_index = generator_get_source(clk_get_generator(index));
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return true;
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}
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if (type == 2 && index == 0) {
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*p_type = 0;
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*p_index = generator_get_source(0);
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return true;
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}
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return false;
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}
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uint32_t clock_get_frequency(uint8_t type, uint8_t index) {
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if (type == 0) {
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return osc_get_frequency(index);
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}
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if (type == 1) {
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if (!clk_enabled(index))
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return 0;
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uint8_t gen = clk_get_generator(index);
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common_hal_mcu_disable_interrupts();
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*((uint8_t*) &GCLK->GENCTRL.reg) = gen;
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*((uint8_t*) &GCLK->GENDIV.reg) = gen;
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while (GCLK->STATUS.bit.SYNCBUSY == 1) {}
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uint8_t src = GCLK->GENCTRL.bit.SRC;
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uint32_t div;
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if (GCLK->GENCTRL.bit.DIVSEL) {
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div = 1 << (GCLK->GENDIV.bit.DIV + 1);
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} else {
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div = GCLK->GENDIV.bit.DIV;
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if (!div)
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div = 1;
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}
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common_hal_mcu_enable_interrupts();
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return osc_get_frequency(src) / div;
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}
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if (type == 2 && index == 0) {
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return clock_get_frequency(0, generator_get_source(0)) / SysTick->LOAD;
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}
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return 0;
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}
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uint32_t clock_get_calibration(uint8_t type, uint8_t index) {
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if (type == 0) {
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switch (index) {
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case GCLK_SOURCE_OSCULP32K:
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return SYSCTRL->OSCULP32K.bit.CALIB;
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case GCLK_SOURCE_OSC32K:
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return SYSCTRL->OSC32K.bit.CALIB;
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case GCLK_SOURCE_OSC8M:
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return SYSCTRL->OSC8M.bit.CALIB;
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};
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}
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if (type == 2 && index == 0) {
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return SysTick->LOAD + 1;
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}
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return 0;
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}
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int clock_set_calibration(uint8_t type, uint8_t index, uint32_t val) {
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if (type == 0) {
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switch (index) {
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case GCLK_SOURCE_OSCULP32K:
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if (val > 0x1f)
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return -1;
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SYSCTRL->OSCULP32K.bit.CALIB = val;
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return 0;
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case GCLK_SOURCE_OSC32K:
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if (val > 0x7f)
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return -1;
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SYSCTRL->OSC32K.bit.CALIB = val;
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return 0;
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case GCLK_SOURCE_OSC8M:
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if (val > 0xfff)
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return -1;
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SYSCTRL->OSC8M.bit.CALIB = val;
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return 0;
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};
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}
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if (type == 2 && index == 0) {
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if (val < 0x1000 || val > 0x1000000)
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return -1;
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SysTick->LOAD = val - 1;
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return 0;
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}
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return -2; // calibration is read only
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}
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#ifdef SAMD21_EXPOSE_ALL_CLOCKS
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CLOCK_SOURCE(XOSC);
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CLOCK_SOURCE(GCLKIN);
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CLOCK_SOURCE(GCLKGEN1);
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CLOCK_SOURCE(OSCULP32K);
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#endif
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CLOCK_SOURCE(OSC32K);
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CLOCK_SOURCE(XOSC32K);
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#ifdef SAMD21_EXPOSE_ALL_CLOCKS
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CLOCK_SOURCE(OSC8M);
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CLOCK_SOURCE(DFLL48M);
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CLOCK_SOURCE(DPLL96M);
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CLOCK_GCLK_(SYSCTRL, DFLL48);
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CLOCK_GCLK_(SYSCTRL, FDPLL);
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CLOCK_GCLK_(SYSCTRL, FDPLL32K);
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CLOCK_GCLK(WDT);
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#endif
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CLOCK_GCLK(RTC);
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#ifdef SAMD21_EXPOSE_ALL_CLOCKS
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CLOCK_GCLK(EIC);
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CLOCK_GCLK(USB);
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CLOCK_GCLK_(EVSYS, 0);
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CLOCK_GCLK_(EVSYS, 1);
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CLOCK_GCLK_(EVSYS, 2);
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CLOCK_GCLK_(EVSYS, 3);
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CLOCK_GCLK_(EVSYS, 4);
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CLOCK_GCLK_(EVSYS, 5);
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CLOCK_GCLK_(EVSYS, 6);
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CLOCK_GCLK_(EVSYS, 7);
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CLOCK_GCLK_(EVSYS, 8);
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CLOCK_GCLK_(EVSYS, 9);
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CLOCK_GCLK_(EVSYS, 10);
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CLOCK_GCLK_(EVSYS, 11);
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CLOCK(SERCOMx_SLOW, 1, 19);
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CLOCK_GCLK_(SERCOM0, CORE);
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CLOCK_GCLK_(SERCOM1, CORE);
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CLOCK_GCLK_(SERCOM2, CORE);
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CLOCK_GCLK_(SERCOM3, CORE);
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CLOCK_GCLK_(SERCOM4, CORE);
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CLOCK_GCLK_(SERCOM5, CORE);
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CLOCK(TCC0_TCC1, 1, 26);
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CLOCK(TCC2_TCC3, 1, 27);
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CLOCK(TC4_TC5, 1, 28);
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CLOCK(TC6_TC7, 1, 29);
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CLOCK_GCLK(ADC);
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CLOCK_GCLK_(AC, DIG);
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CLOCK_GCLK_(AC, ANA);
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CLOCK_GCLK(DAC);
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CLOCK_GCLK(PTC);
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CLOCK_GCLK_(I2S, 0);
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CLOCK_GCLK_(I2S, 1);
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CLOCK(SYSTICK, 2, 0);
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#endif
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STATIC const mp_rom_map_elem_t samd_clock_global_dict_table[] = {
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#ifdef SAMD21_EXPOSE_ALL_CLOCKS
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CLOCK_ENTRY(XOSC),
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CLOCK_ENTRY(GCLKIN),
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CLOCK_ENTRY(GCLKGEN1),
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CLOCK_ENTRY(OSCULP32K),
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#endif
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CLOCK_ENTRY(OSC32K),
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CLOCK_ENTRY(XOSC32K),
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#ifdef SAMD21_EXPOSE_ALL_CLOCKS
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CLOCK_ENTRY(OSC8M),
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CLOCK_ENTRY(DFLL48M),
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CLOCK_ENTRY(DPLL96M),
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CLOCK_ENTRY_(SYSCTRL, DFLL48),
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CLOCK_ENTRY_(SYSCTRL, FDPLL),
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CLOCK_ENTRY_(SYSCTRL, FDPLL32K),
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CLOCK_ENTRY(WDT),
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#endif
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CLOCK_ENTRY(RTC),
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#ifdef SAMD21_EXPOSE_ALL_CLOCKS
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CLOCK_ENTRY(EIC),
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CLOCK_ENTRY(USB),
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CLOCK_ENTRY_(EVSYS, 0),
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CLOCK_ENTRY_(EVSYS, 1),
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CLOCK_ENTRY_(EVSYS, 2),
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CLOCK_ENTRY_(EVSYS, 3),
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CLOCK_ENTRY_(EVSYS, 4),
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CLOCK_ENTRY_(EVSYS, 5),
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CLOCK_ENTRY_(EVSYS, 6),
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CLOCK_ENTRY_(EVSYS, 7),
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CLOCK_ENTRY_(EVSYS, 8),
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CLOCK_ENTRY_(EVSYS, 9),
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CLOCK_ENTRY_(EVSYS, 10),
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CLOCK_ENTRY_(EVSYS, 11),
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CLOCK_ENTRY(SERCOMx_SLOW),
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CLOCK_ENTRY_(SERCOM0, CORE),
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CLOCK_ENTRY_(SERCOM1, CORE),
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CLOCK_ENTRY_(SERCOM2, CORE),
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CLOCK_ENTRY_(SERCOM3, CORE),
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CLOCK_ENTRY_(SERCOM4, CORE),
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CLOCK_ENTRY_(SERCOM5, CORE),
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CLOCK_ENTRY(TCC0_TCC1),
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CLOCK_ENTRY(TCC2_TCC3),
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CLOCK_ENTRY(TC4_TC5),
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CLOCK_ENTRY(TC6_TC7),
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CLOCK_ENTRY(ADC),
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CLOCK_ENTRY_(AC, DIG),
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CLOCK_ENTRY_(AC, ANA),
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CLOCK_ENTRY(DAC),
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CLOCK_ENTRY(PTC),
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CLOCK_ENTRY_(I2S, 0),
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CLOCK_ENTRY_(I2S, 1),
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CLOCK_ENTRY(SYSTICK),
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#endif
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};
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MP_DEFINE_CONST_DICT(samd_clock_globals, samd_clock_global_dict_table);
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