4e25a4f6b3
Doing a squash merge to avoid having the `slc_cli_linux` .zip files in the history. They were added in one commit and removed and replaced with a submodule in another. * Initial commit for xg24 * Fix SLC issue * Fix SLC extract fail * Change board's name * Correct spelling of code Build immediately after slc generate * Remove VID and PID * Change creator and creation id * Apply new creator_id and creation_id * Update makefile, error message, mcu_processor function * Update mpconfigboard.mk * Update Board extensions, PORT_DEPS * Update makefile * Add exclude_patterns * Show java, jinja2 version * Show path for debugging CI * Add requirements-dev for slc * Add PATH slc_cli * Update background function * Add jinja2 PATH * Show PATH * Update jinja2 path * Update jinja2 path * Update jinja2 path * Update jinja2 path * Change slc folder * Change markupsafe folder * Add symbolic link for slc * Update makefile * Update makefile * Update MX25R3235F.toml from submodule nvm.toml * alphabetize the list * Remove slc_cli_linux folder * Update slc_cli submodule --------- Co-authored-by: Chat Nguyen <cvnguyen@silabs.com> Co-authored-by: silabs-ChatNguyen <chat.nguyen@silabs.com> Co-authored-by: silabs-ChatNguyen <126220343+silabs-ChatNguyen@users.noreply.github.com>
224 lines
6.0 KiB
C
224 lines
6.0 KiB
C
/*
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* This file is part of Adafruit for EFR32 project
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*
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* The MIT License (MIT)
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*
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* Copyright 2023 Silicon Laboratories Inc. www.silabs.com
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "py/mphal.h"
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#include "py/obj.h"
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#include "py/runtime.h"
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#include "common-hal/microcontroller/Pin.h"
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#include "common-hal/microcontroller/Processor.h"
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#include "shared-bindings/nvm/ByteArray.h"
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#include "shared-bindings/microcontroller/__init__.h"
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#include "shared-bindings/microcontroller/Pin.h"
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#include "shared-bindings/microcontroller/Processor.h"
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#include "supervisor/filesystem.h"
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#include "supervisor/shared/safe_mode.h"
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#include "em_chip.h"
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#include "em_core.h"
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#include "sl_udelay.h"
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void common_hal_mcu_delay_us(uint32_t delay) {
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sl_udelay_wait(delay);
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}
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void common_hal_mcu_disable_interrupts(void) {
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CORE_CriticalDisableIrq();
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}
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void common_hal_mcu_enable_interrupts(void) {
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CORE_CriticalEnableIrq();
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}
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void common_hal_mcu_on_next_reset(mcu_runmode_t runmode) {
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if (runmode == RUNMODE_SAFE_MODE) {
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safe_mode_on_next_reset(SAFE_MODE_PROGRAMMATIC);
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}
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}
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void common_hal_mcu_reset(void) {
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filesystem_flush(); // TODO: implement as part of flash improvements
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CHIP_Reset();
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}
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// The singleton microcontroller.Processor object, bound to microcontroller.cpu
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// It currently only has properties, and no state.
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const mcu_processor_obj_t common_hal_mcu_processor_obj = {
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.base = {
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.type = &mcu_processor_type,
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},
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};
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#if CIRCUITPY_INTERNAL_NVM_SIZE > 0
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// The singleton nvm.ByteArray object.
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const nvm_bytearray_obj_t common_hal_mcu_nvm_obj = {
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.base = {
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.type = &nvm_bytearray_type,
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},
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.len = NVM_BYTEARRAY_BUFFER_SIZE
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};
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#endif
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#if CIRCUITPY_WATCHDOG
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// The singleton watchdog.WatchDogTimer object.
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watchdog_watchdogtimer_obj_t common_hal_mcu_watchdogtimer_obj = {
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.base = {
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.type = &watchdog_watchdogtimer_type,
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},
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.timeout = 0.0f,
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.mode = WATCHDOGMODE_NONE,
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};
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#endif
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// This maps MCU pin names to pin objects.
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const mp_rom_map_elem_t mcu_pin_global_dict_table[] = {
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#ifdef GPIO_PA0_EXISTS
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{ MP_ROM_QSTR(MP_QSTR_PA0), MP_ROM_PTR(&pin_PA0) },
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#endif
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#ifdef GPIO_PA1_EXISTS
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{ MP_ROM_QSTR(MP_QSTR_PA1), MP_ROM_PTR(&pin_PA1) },
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#endif
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#ifdef GPIO_PA2_EXISTS
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{ MP_ROM_QSTR(MP_QSTR_PA2), MP_ROM_PTR(&pin_PA2) },
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#endif
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#ifdef GPIO_PA3_EXISTS
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{ MP_ROM_QSTR(MP_QSTR_PA3), MP_ROM_PTR(&pin_PA3) },
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#endif
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#ifdef GPIO_PA4_EXISTS
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{ MP_ROM_QSTR(MP_QSTR_PA4), MP_ROM_PTR(&pin_PA4) },
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#endif
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#ifdef GPIO_PA5_EXISTS
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{ MP_ROM_QSTR(MP_QSTR_PA5), MP_ROM_PTR(&pin_PA5) },
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#endif
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#ifdef GPIO_PA6_EXISTS
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{ MP_ROM_QSTR(MP_QSTR_PA6), MP_ROM_PTR(&pin_PA6) },
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#endif
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#ifdef GPIO_PA7_EXISTS
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{ MP_ROM_QSTR(MP_QSTR_PA7), MP_ROM_PTR(&pin_PA7) },
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#endif
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#ifdef GPIO_PA8_EXISTS
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{ MP_ROM_QSTR(MP_QSTR_PA8), MP_ROM_PTR(&pin_PA8) },
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#endif
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#ifdef GPIO_PB0_EXISTS
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{ MP_ROM_QSTR(MP_QSTR_PB0), MP_ROM_PTR(&pin_PB0) },
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#endif
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#ifdef GPIO_PB1_EXISTS
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{ MP_ROM_QSTR(MP_QSTR_PB1), MP_ROM_PTR(&pin_PB1) },
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#endif
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#ifdef GPIO_PB2_EXISTS
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{ MP_ROM_QSTR(MP_QSTR_PB2), MP_ROM_PTR(&pin_PB2) },
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#endif
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#ifdef GPIO_PB3_EXISTS
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{ MP_ROM_QSTR(MP_QSTR_PB3), MP_ROM_PTR(&pin_PB3) },
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#endif
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#ifdef GPIO_PB4_EXISTS
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{ MP_ROM_QSTR(MP_QSTR_PB4), MP_ROM_PTR(&pin_PB4) },
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#endif
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#ifdef GPIO_PB5_EXISTS
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{ MP_ROM_QSTR(MP_QSTR_PB5), MP_ROM_PTR(&pin_PB5) },
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#endif
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#ifdef GPIO_PC0_EXISTS
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{ MP_ROM_QSTR(MP_QSTR_PC0), MP_ROM_PTR(&pin_PC0) },
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#endif
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#ifdef GPIO_PC1_EXISTS
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{ MP_ROM_QSTR(MP_QSTR_PC1), MP_ROM_PTR(&pin_PC1) },
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#endif
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#ifdef GPIO_PC2_EXISTS
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{ MP_ROM_QSTR(MP_QSTR_PC2), MP_ROM_PTR(&pin_PC2) },
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#endif
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#ifdef GPIO_PC3_EXISTS
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{ MP_ROM_QSTR(MP_QSTR_PC3), MP_ROM_PTR(&pin_PC3) },
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#endif
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#ifdef GPIO_PC4_EXISTS
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{ MP_ROM_QSTR(MP_QSTR_PC4), MP_ROM_PTR(&pin_PC4) },
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#endif
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#ifdef GPIO_PC5_EXISTS
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{ MP_ROM_QSTR(MP_QSTR_PC5), MP_ROM_PTR(&pin_PC5) },
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#endif
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#ifdef GPIO_PC6_EXISTS
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{ MP_ROM_QSTR(MP_QSTR_PC6), MP_ROM_PTR(&pin_PC6) },
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#endif
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#ifdef GPIO_PC7_EXISTS
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{ MP_ROM_QSTR(MP_QSTR_PC7), MP_ROM_PTR(&pin_PC7) },
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#endif
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#ifdef GPIO_PC8_EXISTS
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{ MP_ROM_QSTR(MP_QSTR_PC8), MP_ROM_PTR(&pin_PC8) },
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#endif
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#ifdef GPIO_PC9_EXISTS
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{ MP_ROM_QSTR(MP_QSTR_PC9), MP_ROM_PTR(&pin_PC9) },
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#endif
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#ifdef GPIO_PD0_EXISTS
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{ MP_ROM_QSTR(MP_QSTR_PD0), MP_ROM_PTR(&pin_PD0) },
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#endif
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#ifdef GPIO_PD1_EXISTS
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{ MP_ROM_QSTR(MP_QSTR_PD1), MP_ROM_PTR(&pin_PD1) },
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#endif
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#ifdef GPIO_PD2_EXISTS
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{ MP_ROM_QSTR(MP_QSTR_PD2), MP_ROM_PTR(&pin_PD2) },
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#endif
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#ifdef GPIO_PD3_EXISTS
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{ MP_ROM_QSTR(MP_QSTR_PD3), MP_ROM_PTR(&pin_PD3) },
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#endif
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#ifdef GPIO_PD4_EXISTS
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{ MP_ROM_QSTR(MP_QSTR_PD4), MP_ROM_PTR(&pin_PD4) },
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#endif
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#ifdef GPIO_PD5_EXISTS
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{ MP_ROM_QSTR(MP_QSTR_PD5), MP_ROM_PTR(&pin_PD5) }
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#endif
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};
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MP_DEFINE_CONST_DICT(mcu_pin_globals, mcu_pin_global_dict_table);
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