1874 lines
76 KiB
C
1874 lines
76 KiB
C
/**
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******************************************************************************
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* @file stm32f4xx_rcc.c
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* @author MCD Application Team
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* @version V1.1.0
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* @date 11-January-2013
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* @brief This file provides firmware functions to manage the following
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* functionalities of the Reset and clock control (RCC) peripheral:
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* + Internal/external clocks, PLL, CSS and MCO configuration
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* + System, AHB and APB busses clocks configuration
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* + Peripheral clocks configuration
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* + Interrupts and flags management
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*
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@verbatim
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===============================================================================
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##### RCC specific features #####
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===============================================================================
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[..]
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After reset the device is running from Internal High Speed oscillator
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(HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache
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and I-Cache are disabled, and all peripherals are off except internal
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SRAM, Flash and JTAG.
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(+) There is no prescaler on High speed (AHB) and Low speed (APB) busses;
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all peripherals mapped on these busses are running at HSI speed.
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(+) The clock for all peripherals is switched off, except the SRAM and FLASH.
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(+) All GPIOs are in input floating state, except the JTAG pins which
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are assigned to be used for debug purpose.
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[..]
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Once the device started from reset, the user application has to:
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(+) Configure the clock source to be used to drive the System clock
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(if the application needs higher frequency/performance)
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(+) Configure the System clock frequency and Flash settings
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(+) Configure the AHB and APB busses prescalers
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(+) Enable the clock for the peripheral(s) to be used
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(+) Configure the clock source(s) for peripherals which clocks are not
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derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG)
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@endverbatim
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>
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*
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* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
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* You may not use this file except in compliance with the License.
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* You may obtain a copy of the License at:
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*
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* http://www.st.com/software_license_agreement_liberty_v2
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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******************************************************************************
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*/
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/* Includes ------------------------------------------------------------------*/
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#include "stm32f4xx_rcc.h"
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#include "stm32f4xx_conf.h"
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/** @addtogroup STM32F4xx_StdPeriph_Driver
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* @{
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*/
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/** @defgroup RCC
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* @brief RCC driver modules
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* @{
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*/
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/* Private typedef -----------------------------------------------------------*/
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/* Private define ------------------------------------------------------------*/
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/* ------------ RCC registers bit address in the alias region ----------- */
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#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
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/* --- CR Register ---*/
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/* Alias word address of HSION bit */
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#define CR_OFFSET (RCC_OFFSET + 0x00)
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#define HSION_BitNumber 0x00
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#define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4))
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/* Alias word address of CSSON bit */
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#define CSSON_BitNumber 0x13
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#define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4))
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/* Alias word address of PLLON bit */
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#define PLLON_BitNumber 0x18
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#define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4))
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/* Alias word address of PLLI2SON bit */
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#define PLLI2SON_BitNumber 0x1A
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#define CR_PLLI2SON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLI2SON_BitNumber * 4))
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/* --- CFGR Register ---*/
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/* Alias word address of I2SSRC bit */
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#define CFGR_OFFSET (RCC_OFFSET + 0x08)
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#define I2SSRC_BitNumber 0x17
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#define CFGR_I2SSRC_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (I2SSRC_BitNumber * 4))
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/* --- BDCR Register ---*/
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/* Alias word address of RTCEN bit */
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#define BDCR_OFFSET (RCC_OFFSET + 0x70)
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#define RTCEN_BitNumber 0x0F
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#define BDCR_RTCEN_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4))
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/* Alias word address of BDRST bit */
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#define BDRST_BitNumber 0x10
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#define BDCR_BDRST_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4))
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/* --- CSR Register ---*/
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/* Alias word address of LSION bit */
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#define CSR_OFFSET (RCC_OFFSET + 0x74)
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#define LSION_BitNumber 0x00
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#define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4))
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/* --- DCKCFGR Register ---*/
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/* Alias word address of TIMPRE bit */
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#define DCKCFGR_OFFSET (RCC_OFFSET + 0x8C)
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#define TIMPRE_BitNumber 0x18
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#define DCKCFGR_TIMPRE_BB (PERIPH_BB_BASE + (DCKCFGR_OFFSET * 32) + (TIMPRE_BitNumber * 4))
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/* ---------------------- RCC registers bit mask ------------------------ */
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/* CFGR register bit mask */
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#define CFGR_MCO2_RESET_MASK ((uint32_t)0x07FFFFFF)
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#define CFGR_MCO1_RESET_MASK ((uint32_t)0xF89FFFFF)
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/* RCC Flag Mask */
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#define FLAG_MASK ((uint8_t)0x1F)
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/* CR register byte 3 (Bits[23:16]) base address */
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#define CR_BYTE3_ADDRESS ((uint32_t)0x40023802)
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/* CIR register byte 2 (Bits[15:8]) base address */
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#define CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x01))
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/* CIR register byte 3 (Bits[23:16]) base address */
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#define CIR_BYTE3_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x02))
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/* BDCR register base address */
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#define BDCR_ADDRESS (PERIPH_BASE + BDCR_OFFSET)
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/* Private macro -------------------------------------------------------------*/
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/* Private variables ---------------------------------------------------------*/
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static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
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/* Private function prototypes -----------------------------------------------*/
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/* Private functions ---------------------------------------------------------*/
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/** @defgroup RCC_Private_Functions
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* @{
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*/
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/** @defgroup RCC_Group1 Internal and external clocks, PLL, CSS and MCO configuration functions
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* @brief Internal and external clocks, PLL, CSS and MCO configuration functions
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*
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@verbatim
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===================================================================================
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##### Internal and external clocks, PLL, CSS and MCO configuration functions #####
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===================================================================================
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[..]
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This section provide functions allowing to configure the internal/external clocks,
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PLLs, CSS and MCO pins.
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(#) HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through
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the PLL as System clock source.
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(#) LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC
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clock source.
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(#) HSE (high-speed external), 4 to 26 MHz crystal oscillator used directly or
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through the PLL as System clock source. Can be used also as RTC clock source.
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(#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
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(#) PLL (clocked by HSI or HSE), featuring two different output clocks:
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(++) The first output is used to generate the high speed system clock (up to 168 MHz)
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(++) The second output is used to generate the clock for the USB OTG FS (48 MHz),
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the random analog generator (<=48 MHz) and the SDIO (<= 48 MHz).
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(#) PLLI2S (clocked by HSI or HSE), used to generate an accurate clock to achieve
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high-quality audio performance on the I2S interface.
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(#) CSS (Clock security system), once enable and if a HSE clock failure occurs
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(HSE used directly or through PLL as System clock source), the System clock
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is automatically switched to HSI and an interrupt is generated if enabled.
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The interrupt is linked to the Cortex-M4 NMI (Non-Maskable Interrupt)
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exception vector.
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(#) MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or PLL
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clock (through a configurable prescaler) on PA8 pin.
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(#) MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or PLLI2S
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clock (through a configurable prescaler) on PC9 pin.
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@endverbatim
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* @{
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*/
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/**
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* @brief Resets the RCC clock configuration to the default reset state.
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* @note The default reset state of the clock configuration is given below:
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* - HSI ON and used as system clock source
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* - HSE, PLL and PLLI2S OFF
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* - AHB, APB1 and APB2 prescaler set to 1.
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* - CSS, MCO1 and MCO2 OFF
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* - All interrupts disabled
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* @note This function doesn't modify the configuration of the
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* - Peripheral clocks
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* - LSI, LSE and RTC clocks
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* @param None
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* @retval None
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*/
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void RCC_DeInit(void)
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{
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/* Set HSION bit */
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RCC->CR |= (uint32_t)0x00000001;
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/* Reset CFGR register */
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RCC->CFGR = 0x00000000;
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/* Reset HSEON, CSSON, PLLON and PLLI2S bits */
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RCC->CR &= (uint32_t)0xFAF6FFFF;
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/* Reset PLLCFGR register */
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RCC->PLLCFGR = 0x24003010;
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/* Reset PLLI2SCFGR register */
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RCC->PLLI2SCFGR = 0x20003000;
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/* Reset HSEBYP bit */
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RCC->CR &= (uint32_t)0xFFFBFFFF;
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/* Disable all interrupts */
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RCC->CIR = 0x00000000;
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#ifdef STM32F427X
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/* Disable Timers clock prescalers selection */
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RCC->DCKCFGR = 0x00000000;
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#endif /* STM32F427X */
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}
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/**
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* @brief Configures the External High Speed oscillator (HSE).
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* @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
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* software should wait on HSERDY flag to be set indicating that HSE clock
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* is stable and can be used to clock the PLL and/or system clock.
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* @note HSE state can not be changed if it is used directly or through the
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* PLL as system clock. In this case, you have to select another source
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* of the system clock then change the HSE state (ex. disable it).
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* @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
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* @note This function reset the CSSON bit, so if the Clock security system(CSS)
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* was previously enabled you have to enable it again after calling this
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* function.
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* @param RCC_HSE: specifies the new state of the HSE.
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* This parameter can be one of the following values:
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* @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
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* 6 HSE oscillator clock cycles.
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* @arg RCC_HSE_ON: turn ON the HSE oscillator
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* @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock
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* @retval None
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*/
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void RCC_HSEConfig(uint8_t RCC_HSE)
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{
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/* Check the parameters */
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assert_param(IS_RCC_HSE(RCC_HSE));
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/* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/
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*(__IO uint8_t *) CR_BYTE3_ADDRESS = RCC_HSE_OFF;
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/* Set the new HSE configuration -------------------------------------------*/
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*(__IO uint8_t *) CR_BYTE3_ADDRESS = RCC_HSE;
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}
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/**
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* @brief Waits for HSE start-up.
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* @note This functions waits on HSERDY flag to be set and return SUCCESS if
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* this flag is set, otherwise returns ERROR if the timeout is reached
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* and this flag is not set. The timeout value is defined by the constant
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* HSE_STARTUP_TIMEOUT in stm32f4xx.h file. You can tailor it depending
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* on the HSE crystal used in your application.
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* @param None
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* @retval An ErrorStatus enumeration value:
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* - SUCCESS: HSE oscillator is stable and ready to use
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* - ERROR: HSE oscillator not yet ready
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*/
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ErrorStatus RCC_WaitForHSEStartUp(void)
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{
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__IO uint32_t startupcounter = 0;
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ErrorStatus status = ERROR;
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FlagStatus hsestatus = RESET;
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/* Wait till HSE is ready and if Time out is reached exit */
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do
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{
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hsestatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY);
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startupcounter++;
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} while((startupcounter != HSE_STARTUP_TIMEOUT) && (hsestatus == RESET));
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if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET)
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{
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status = SUCCESS;
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}
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else
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{
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status = ERROR;
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}
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return (status);
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}
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/**
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* @brief Adjusts the Internal High Speed oscillator (HSI) calibration value.
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* @note The calibration is used to compensate for the variations in voltage
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* and temperature that influence the frequency of the internal HSI RC.
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* @param HSICalibrationValue: specifies the calibration trimming value.
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* This parameter must be a number between 0 and 0x1F.
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* @retval None
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*/
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void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue)
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{
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uint32_t tmpreg = 0;
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/* Check the parameters */
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assert_param(IS_RCC_CALIBRATION_VALUE(HSICalibrationValue));
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tmpreg = RCC->CR;
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/* Clear HSITRIM[4:0] bits */
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tmpreg &= ~RCC_CR_HSITRIM;
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/* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */
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tmpreg |= (uint32_t)HSICalibrationValue << 3;
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/* Store the new value */
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RCC->CR = tmpreg;
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}
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/**
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* @brief Enables or disables the Internal High Speed oscillator (HSI).
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* @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
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* It is used (enabled by hardware) as system clock source after startup
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* from Reset, wakeup from STOP and STANDBY mode, or in case of failure
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* of the HSE used directly or indirectly as system clock (if the Clock
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* Security System CSS is enabled).
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* @note HSI can not be stopped if it is used as system clock source. In this case,
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* you have to select another source of the system clock then stop the HSI.
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* @note After enabling the HSI, the application software should wait on HSIRDY
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* flag to be set indicating that HSI clock is stable and can be used as
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* system clock source.
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* @param NewState: new state of the HSI.
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* This parameter can be: ENABLE or DISABLE.
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* @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
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* clock cycles.
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* @retval None
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*/
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void RCC_HSICmd(FunctionalState NewState)
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{
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/* Check the parameters */
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assert_param(IS_FUNCTIONAL_STATE(NewState));
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*(__IO uint32_t *) CR_HSION_BB = (uint32_t)NewState;
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}
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/**
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* @brief Configures the External Low Speed oscillator (LSE).
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* @note As the LSE is in the Backup domain and write access is denied to
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* this domain after reset, you have to enable write access using
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* PWR_BackupAccessCmd(ENABLE) function before to configure the LSE
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* (to be done once after reset).
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* @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_Bypass), the application
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* software should wait on LSERDY flag to be set indicating that LSE clock
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* is stable and can be used to clock the RTC.
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* @param RCC_LSE: specifies the new state of the LSE.
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* This parameter can be one of the following values:
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* @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
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* 6 LSE oscillator clock cycles.
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* @arg RCC_LSE_ON: turn ON the LSE oscillator
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* @arg RCC_LSE_Bypass: LSE oscillator bypassed with external clock
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* @retval None
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*/
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void RCC_LSEConfig(uint8_t RCC_LSE)
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{
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/* Check the parameters */
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assert_param(IS_RCC_LSE(RCC_LSE));
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/* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/
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/* Reset LSEON bit */
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*(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF;
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/* Reset LSEBYP bit */
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*(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF;
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/* Configure LSE (RCC_LSE_OFF is already covered by the code section above) */
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switch (RCC_LSE)
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{
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case RCC_LSE_ON:
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/* Set LSEON bit */
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*(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_ON;
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break;
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case RCC_LSE_Bypass:
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/* Set LSEBYP and LSEON bits */
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*(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON;
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break;
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default:
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break;
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}
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}
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/**
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* @brief Enables or disables the Internal Low Speed oscillator (LSI).
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* @note After enabling the LSI, the application software should wait on
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* LSIRDY flag to be set indicating that LSI clock is stable and can
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* be used to clock the IWDG and/or the RTC.
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* @note LSI can not be disabled if the IWDG is running.
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* @param NewState: new state of the LSI.
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* This parameter can be: ENABLE or DISABLE.
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* @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
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* clock cycles.
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* @retval None
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*/
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void RCC_LSICmd(FunctionalState NewState)
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{
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/* Check the parameters */
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assert_param(IS_FUNCTIONAL_STATE(NewState));
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*(__IO uint32_t *) CSR_LSION_BB = (uint32_t)NewState;
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}
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/**
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* @brief Configures the main PLL clock source, multiplication and division factors.
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* @note This function must be used only when the main PLL is disabled.
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*
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* @param RCC_PLLSource: specifies the PLL entry clock source.
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* This parameter can be one of the following values:
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* @arg RCC_PLLSource_HSI: HSI oscillator clock selected as PLL clock entry
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* @arg RCC_PLLSource_HSE: HSE oscillator clock selected as PLL clock entry
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* @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
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*
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* @param PLLM: specifies the division factor for PLL VCO input clock
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* This parameter must be a number between 0 and 63.
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* @note You have to set the PLLM parameter correctly to ensure that the VCO input
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* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
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* of 2 MHz to limit PLL jitter.
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*
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* @param PLLN: specifies the multiplication factor for PLL VCO output clock
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* This parameter must be a number between 192 and 432.
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* @note You have to set the PLLN parameter correctly to ensure that the VCO
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* output frequency is between 192 and 432 MHz.
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*
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* @param PLLP: specifies the division factor for main system clock (SYSCLK)
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* This parameter must be a number in the range {2, 4, 6, or 8}.
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* @note You have to set the PLLP parameter correctly to not exceed 168 MHz on
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* the System clock frequency.
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*
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* @param PLLQ: specifies the division factor for OTG FS, SDIO and RNG clocks
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* This parameter must be a number between 4 and 15.
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* @note If the USB OTG FS is used in your application, you have to set the
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* PLLQ parameter correctly to have 48 MHz clock for the USB. However,
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* the SDIO and RNG need a frequency lower than or equal to 48 MHz to work
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|
* correctly.
|
|
*
|
|
* @retval None
|
|
*/
|
|
void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ)
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource));
|
|
assert_param(IS_RCC_PLLM_VALUE(PLLM));
|
|
assert_param(IS_RCC_PLLN_VALUE(PLLN));
|
|
assert_param(IS_RCC_PLLP_VALUE(PLLP));
|
|
assert_param(IS_RCC_PLLQ_VALUE(PLLQ));
|
|
|
|
RCC->PLLCFGR = PLLM | (PLLN << 6) | (((PLLP >> 1) -1) << 16) | (RCC_PLLSource) |
|
|
(PLLQ << 24);
|
|
}
|
|
|
|
/**
|
|
* @brief Enables or disables the main PLL.
|
|
* @note After enabling the main PLL, the application software should wait on
|
|
* PLLRDY flag to be set indicating that PLL clock is stable and can
|
|
* be used as system clock source.
|
|
* @note The main PLL can not be disabled if it is used as system clock source
|
|
* @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
|
|
* @param NewState: new state of the main PLL. This parameter can be: ENABLE or DISABLE.
|
|
* @retval None
|
|
*/
|
|
void RCC_PLLCmd(FunctionalState NewState)
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
|
*(__IO uint32_t *) CR_PLLON_BB = (uint32_t)NewState;
|
|
}
|
|
|
|
/**
|
|
* @brief Configures the PLLI2S clock multiplication and division factors.
|
|
*
|
|
* @note This function must be used only when the PLLI2S is disabled.
|
|
* @note PLLI2S clock source is common with the main PLL (configured in
|
|
* RCC_PLLConfig function )
|
|
*
|
|
* @param PLLI2SN: specifies the multiplication factor for PLLI2S VCO output clock
|
|
* This parameter must be a number between 192 and 432.
|
|
* @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
|
|
* output frequency is between 192 and 432 MHz.
|
|
*
|
|
* @param PLLI2SR: specifies the division factor for I2S clock
|
|
* This parameter must be a number between 2 and 7.
|
|
* @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
|
|
* on the I2S clock frequency.
|
|
*
|
|
* @retval None
|
|
*/
|
|
void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR)
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_PLLI2SN_VALUE(PLLI2SN));
|
|
assert_param(IS_RCC_PLLI2SR_VALUE(PLLI2SR));
|
|
|
|
RCC->PLLI2SCFGR = (PLLI2SN << 6) | (PLLI2SR << 28);
|
|
}
|
|
|
|
/**
|
|
* @brief Enables or disables the PLLI2S.
|
|
* @note The PLLI2S is disabled by hardware when entering STOP and STANDBY modes.
|
|
* @param NewState: new state of the PLLI2S. This parameter can be: ENABLE or DISABLE.
|
|
* @retval None
|
|
*/
|
|
void RCC_PLLI2SCmd(FunctionalState NewState)
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
|
*(__IO uint32_t *) CR_PLLI2SON_BB = (uint32_t)NewState;
|
|
}
|
|
|
|
/**
|
|
* @brief Enables or disables the Clock Security System.
|
|
* @note If a failure is detected on the HSE oscillator clock, this oscillator
|
|
* is automatically disabled and an interrupt is generated to inform the
|
|
* software about the failure (Clock Security System Interrupt, CSSI),
|
|
* allowing the MCU to perform rescue operations. The CSSI is linked to
|
|
* the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector.
|
|
* @param NewState: new state of the Clock Security System.
|
|
* This parameter can be: ENABLE or DISABLE.
|
|
* @retval None
|
|
*/
|
|
void RCC_ClockSecuritySystemCmd(FunctionalState NewState)
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
|
*(__IO uint32_t *) CR_CSSON_BB = (uint32_t)NewState;
|
|
}
|
|
|
|
/**
|
|
* @brief Selects the clock source to output on MCO1 pin(PA8).
|
|
* @note PA8 should be configured in alternate function mode.
|
|
* @param RCC_MCO1Source: specifies the clock source to output.
|
|
* This parameter can be one of the following values:
|
|
* @arg RCC_MCO1Source_HSI: HSI clock selected as MCO1 source
|
|
* @arg RCC_MCO1Source_LSE: LSE clock selected as MCO1 source
|
|
* @arg RCC_MCO1Source_HSE: HSE clock selected as MCO1 source
|
|
* @arg RCC_MCO1Source_PLLCLK: main PLL clock selected as MCO1 source
|
|
* @param RCC_MCO1Div: specifies the MCO1 prescaler.
|
|
* This parameter can be one of the following values:
|
|
* @arg RCC_MCO1Div_1: no division applied to MCO1 clock
|
|
* @arg RCC_MCO1Div_2: division by 2 applied to MCO1 clock
|
|
* @arg RCC_MCO1Div_3: division by 3 applied to MCO1 clock
|
|
* @arg RCC_MCO1Div_4: division by 4 applied to MCO1 clock
|
|
* @arg RCC_MCO1Div_5: division by 5 applied to MCO1 clock
|
|
* @retval None
|
|
*/
|
|
void RCC_MCO1Config(uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div)
|
|
{
|
|
uint32_t tmpreg = 0;
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_MCO1SOURCE(RCC_MCO1Source));
|
|
assert_param(IS_RCC_MCO1DIV(RCC_MCO1Div));
|
|
|
|
tmpreg = RCC->CFGR;
|
|
|
|
/* Clear MCO1[1:0] and MCO1PRE[2:0] bits */
|
|
tmpreg &= CFGR_MCO1_RESET_MASK;
|
|
|
|
/* Select MCO1 clock source and prescaler */
|
|
tmpreg |= RCC_MCO1Source | RCC_MCO1Div;
|
|
|
|
/* Store the new value */
|
|
RCC->CFGR = tmpreg;
|
|
}
|
|
|
|
/**
|
|
* @brief Selects the clock source to output on MCO2 pin(PC9).
|
|
* @note PC9 should be configured in alternate function mode.
|
|
* @param RCC_MCO2Source: specifies the clock source to output.
|
|
* This parameter can be one of the following values:
|
|
* @arg RCC_MCO2Source_SYSCLK: System clock (SYSCLK) selected as MCO2 source
|
|
* @arg RCC_MCO2Source_PLLI2SCLK: PLLI2S clock selected as MCO2 source
|
|
* @arg RCC_MCO2Source_HSE: HSE clock selected as MCO2 source
|
|
* @arg RCC_MCO2Source_PLLCLK: main PLL clock selected as MCO2 source
|
|
* @param RCC_MCO2Div: specifies the MCO2 prescaler.
|
|
* This parameter can be one of the following values:
|
|
* @arg RCC_MCO2Div_1: no division applied to MCO2 clock
|
|
* @arg RCC_MCO2Div_2: division by 2 applied to MCO2 clock
|
|
* @arg RCC_MCO2Div_3: division by 3 applied to MCO2 clock
|
|
* @arg RCC_MCO2Div_4: division by 4 applied to MCO2 clock
|
|
* @arg RCC_MCO2Div_5: division by 5 applied to MCO2 clock
|
|
* @retval None
|
|
*/
|
|
void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div)
|
|
{
|
|
uint32_t tmpreg = 0;
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_MCO2SOURCE(RCC_MCO2Source));
|
|
assert_param(IS_RCC_MCO2DIV(RCC_MCO2Div));
|
|
|
|
tmpreg = RCC->CFGR;
|
|
|
|
/* Clear MCO2 and MCO2PRE[2:0] bits */
|
|
tmpreg &= CFGR_MCO2_RESET_MASK;
|
|
|
|
/* Select MCO2 clock source and prescaler */
|
|
tmpreg |= RCC_MCO2Source | RCC_MCO2Div;
|
|
|
|
/* Store the new value */
|
|
RCC->CFGR = tmpreg;
|
|
}
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup RCC_Group2 System AHB and APB busses clocks configuration functions
|
|
* @brief System, AHB and APB busses clocks configuration functions
|
|
*
|
|
@verbatim
|
|
===============================================================================
|
|
##### System, AHB and APB busses clocks configuration functions #####
|
|
===============================================================================
|
|
[..]
|
|
This section provide functions allowing to configure the System, AHB, APB1 and
|
|
APB2 busses clocks.
|
|
|
|
(#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
|
|
HSE and PLL.
|
|
The AHB clock (HCLK) is derived from System clock through configurable
|
|
prescaler and used to clock the CPU, memory and peripherals mapped
|
|
on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived
|
|
from AHB clock through configurable prescalers and used to clock
|
|
the peripherals mapped on these busses. You can use
|
|
"RCC_GetClocksFreq()" function to retrieve the frequencies of these clocks.
|
|
|
|
-@- All the peripheral clocks are derived from the System clock (SYSCLK) except:
|
|
(+@) I2S: the I2S clock can be derived either from a specific PLL (PLLI2S) or
|
|
from an external clock mapped on the I2S_CKIN pin.
|
|
You have to use RCC_I2SCLKConfig() function to configure this clock.
|
|
(+@) RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock
|
|
divided by 2 to 31. You have to use RCC_RTCCLKConfig() and RCC_RTCCLKCmd()
|
|
functions to configure this clock.
|
|
(+@) USB OTG FS, SDIO and RTC: USB OTG FS require a frequency equal to 48 MHz
|
|
to work correctly, while the SDIO require a frequency equal or lower than
|
|
to 48. This clock is derived of the main PLL through PLLQ divider.
|
|
(+@) IWDG clock which is always the LSI clock.
|
|
|
|
(#) The maximum frequency of the SYSCLK and HCLK is 168 MHz, PCLK2 84 MHz
|
|
and PCLK1 42 MHz. Depending on the device voltage range, the maximum
|
|
frequency should be adapted accordingly:
|
|
+-------------------------------------------------------------------------------------+
|
|
| Latency | HCLK clock frequency (MHz) |
|
|
| |---------------------------------------------------------------------|
|
|
| | voltage range | voltage range | voltage range | voltage range |
|
|
| | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V |
|
|
|---------------|----------------|----------------|-----------------|-----------------|
|
|
|0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 18 |0 < HCLK <= 16 |
|
|
|---------------|----------------|----------------|-----------------|-----------------|
|
|
|1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |18 < HCLK <= 36 |16 < HCLK <= 32 |
|
|
|---------------|----------------|----------------|-----------------|-----------------|
|
|
|2WS(3CPU cycle)|60 < HCLK <= 90 |48 < HCLK <= 72 |36 < HCLK <= 54 |32 < HCLK <= 48 |
|
|
|---------------|----------------|----------------|-----------------|-----------------|
|
|
|3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |54 < HCLK <= 72 |48 < HCLK <= 64 |
|
|
|---------------|----------------|----------------|-----------------|-----------------|
|
|
|4WS(5CPU cycle)|120< HCLK <= 150|96 < HCLK <= 120|72 < HCLK <= 90 |64 < HCLK <= 80 |
|
|
|---------------|----------------|----------------|-----------------|-----------------|
|
|
|5WS(6CPU cycle)|120< HCLK <= 168|120< HCLK <= 144|90 < HCLK <= 108 |80 < HCLK <= 96 |
|
|
|---------------|----------------|----------------|-----------------|-----------------|
|
|
|6WS(7CPU cycle)| NA |144< HCLK <= 168|108 < HCLK <= 120|96 < HCLK <= 112 |
|
|
|---------------|----------------|----------------|-----------------|-----------------|
|
|
|7WS(8CPU cycle)| NA | NA |120 < HCLK <= 138|112 < HCLK <= 120|
|
|
+-------------------------------------------------------------------------------------+
|
|
-@- When VOS bits (in PWR_CR register) is reset to 0 , the maximum value of HCLK is 144 MHz.
|
|
You can use PWR_MainRegulatorModeConfig() function to set or reset this bit.
|
|
|
|
@endverbatim
|
|
* @{
|
|
*/
|
|
|
|
/**
|
|
* @brief Configures the system clock (SYSCLK).
|
|
* @note The HSI is used (enabled by hardware) as system clock source after
|
|
* startup from Reset, wake-up from STOP and STANDBY mode, or in case
|
|
* of failure of the HSE used directly or indirectly as system clock
|
|
* (if the Clock Security System CSS is enabled).
|
|
* @note A switch from one clock source to another occurs only if the target
|
|
* clock source is ready (clock stable after startup delay or PLL locked).
|
|
* If a clock source which is not yet ready is selected, the switch will
|
|
* occur when the clock source will be ready.
|
|
* You can use RCC_GetSYSCLKSource() function to know which clock is
|
|
* currently used as system clock source.
|
|
* @param RCC_SYSCLKSource: specifies the clock source used as system clock.
|
|
* This parameter can be one of the following values:
|
|
* @arg RCC_SYSCLKSource_HSI: HSI selected as system clock source
|
|
* @arg RCC_SYSCLKSource_HSE: HSE selected as system clock source
|
|
* @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock source
|
|
* @retval None
|
|
*/
|
|
void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)
|
|
{
|
|
uint32_t tmpreg = 0;
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource));
|
|
|
|
tmpreg = RCC->CFGR;
|
|
|
|
/* Clear SW[1:0] bits */
|
|
tmpreg &= ~RCC_CFGR_SW;
|
|
|
|
/* Set SW[1:0] bits according to RCC_SYSCLKSource value */
|
|
tmpreg |= RCC_SYSCLKSource;
|
|
|
|
/* Store the new value */
|
|
RCC->CFGR = tmpreg;
|
|
}
|
|
|
|
/**
|
|
* @brief Returns the clock source used as system clock.
|
|
* @param None
|
|
* @retval The clock source used as system clock. The returned value can be one
|
|
* of the following:
|
|
* - 0x00: HSI used as system clock
|
|
* - 0x04: HSE used as system clock
|
|
* - 0x08: PLL used as system clock
|
|
*/
|
|
uint8_t RCC_GetSYSCLKSource(void)
|
|
{
|
|
return ((uint8_t)(RCC->CFGR & RCC_CFGR_SWS));
|
|
}
|
|
|
|
/**
|
|
* @brief Configures the AHB clock (HCLK).
|
|
* @note Depending on the device voltage range, the software has to set correctly
|
|
* these bits to ensure that HCLK not exceed the maximum allowed frequency
|
|
* (for more details refer to section above
|
|
* "CPU, AHB and APB busses clocks configuration functions")
|
|
* @param RCC_SYSCLK: defines the AHB clock divider. This clock is derived from
|
|
* the system clock (SYSCLK).
|
|
* This parameter can be one of the following values:
|
|
* @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK
|
|
* @arg RCC_SYSCLK_Div2: AHB clock = SYSCLK/2
|
|
* @arg RCC_SYSCLK_Div4: AHB clock = SYSCLK/4
|
|
* @arg RCC_SYSCLK_Div8: AHB clock = SYSCLK/8
|
|
* @arg RCC_SYSCLK_Div16: AHB clock = SYSCLK/16
|
|
* @arg RCC_SYSCLK_Div64: AHB clock = SYSCLK/64
|
|
* @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128
|
|
* @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256
|
|
* @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512
|
|
* @retval None
|
|
*/
|
|
void RCC_HCLKConfig(uint32_t RCC_SYSCLK)
|
|
{
|
|
uint32_t tmpreg = 0;
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_HCLK(RCC_SYSCLK));
|
|
|
|
tmpreg = RCC->CFGR;
|
|
|
|
/* Clear HPRE[3:0] bits */
|
|
tmpreg &= ~RCC_CFGR_HPRE;
|
|
|
|
/* Set HPRE[3:0] bits according to RCC_SYSCLK value */
|
|
tmpreg |= RCC_SYSCLK;
|
|
|
|
/* Store the new value */
|
|
RCC->CFGR = tmpreg;
|
|
}
|
|
|
|
|
|
/**
|
|
* @brief Configures the Low Speed APB clock (PCLK1).
|
|
* @param RCC_HCLK: defines the APB1 clock divider. This clock is derived from
|
|
* the AHB clock (HCLK).
|
|
* This parameter can be one of the following values:
|
|
* @arg RCC_HCLK_Div1: APB1 clock = HCLK
|
|
* @arg RCC_HCLK_Div2: APB1 clock = HCLK/2
|
|
* @arg RCC_HCLK_Div4: APB1 clock = HCLK/4
|
|
* @arg RCC_HCLK_Div8: APB1 clock = HCLK/8
|
|
* @arg RCC_HCLK_Div16: APB1 clock = HCLK/16
|
|
* @retval None
|
|
*/
|
|
void RCC_PCLK1Config(uint32_t RCC_HCLK)
|
|
{
|
|
uint32_t tmpreg = 0;
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_PCLK(RCC_HCLK));
|
|
|
|
tmpreg = RCC->CFGR;
|
|
|
|
/* Clear PPRE1[2:0] bits */
|
|
tmpreg &= ~RCC_CFGR_PPRE1;
|
|
|
|
/* Set PPRE1[2:0] bits according to RCC_HCLK value */
|
|
tmpreg |= RCC_HCLK;
|
|
|
|
/* Store the new value */
|
|
RCC->CFGR = tmpreg;
|
|
}
|
|
|
|
/**
|
|
* @brief Configures the High Speed APB clock (PCLK2).
|
|
* @param RCC_HCLK: defines the APB2 clock divider. This clock is derived from
|
|
* the AHB clock (HCLK).
|
|
* This parameter can be one of the following values:
|
|
* @arg RCC_HCLK_Div1: APB2 clock = HCLK
|
|
* @arg RCC_HCLK_Div2: APB2 clock = HCLK/2
|
|
* @arg RCC_HCLK_Div4: APB2 clock = HCLK/4
|
|
* @arg RCC_HCLK_Div8: APB2 clock = HCLK/8
|
|
* @arg RCC_HCLK_Div16: APB2 clock = HCLK/16
|
|
* @retval None
|
|
*/
|
|
void RCC_PCLK2Config(uint32_t RCC_HCLK)
|
|
{
|
|
uint32_t tmpreg = 0;
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_PCLK(RCC_HCLK));
|
|
|
|
tmpreg = RCC->CFGR;
|
|
|
|
/* Clear PPRE2[2:0] bits */
|
|
tmpreg &= ~RCC_CFGR_PPRE2;
|
|
|
|
/* Set PPRE2[2:0] bits according to RCC_HCLK value */
|
|
tmpreg |= RCC_HCLK << 3;
|
|
|
|
/* Store the new value */
|
|
RCC->CFGR = tmpreg;
|
|
}
|
|
|
|
/**
|
|
* @brief Returns the frequencies of different on chip clocks; SYSCLK, HCLK,
|
|
* PCLK1 and PCLK2.
|
|
*
|
|
* @note The system frequency computed by this function is not the real
|
|
* frequency in the chip. It is calculated based on the predefined
|
|
* constant and the selected clock source:
|
|
* @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
|
|
* @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
|
|
* @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**)
|
|
* or HSI_VALUE(*) multiplied/divided by the PLL factors.
|
|
* @note (*) HSI_VALUE is a constant defined in stm32f4xx.h file (default value
|
|
* 16 MHz) but the real value may vary depending on the variations
|
|
* in voltage and temperature.
|
|
* @note (**) HSE_VALUE is a constant defined in stm32f4xx.h file (default value
|
|
* 25 MHz), user has to ensure that HSE_VALUE is same as the real
|
|
* frequency of the crystal used. Otherwise, this function may
|
|
* have wrong result.
|
|
*
|
|
* @note The result of this function could be not correct when using fractional
|
|
* value for HSE crystal.
|
|
*
|
|
* @param RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold
|
|
* the clocks frequencies.
|
|
*
|
|
* @note This function can be used by the user application to compute the
|
|
* baudrate for the communication peripherals or configure other parameters.
|
|
* @note Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function
|
|
* must be called to update the structure's field. Otherwise, any
|
|
* configuration based on this function will be incorrect.
|
|
*
|
|
* @retval None
|
|
*/
|
|
void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
|
|
{
|
|
uint32_t tmp = 0, presc = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
|
|
|
|
/* Get SYSCLK source -------------------------------------------------------*/
|
|
tmp = RCC->CFGR & RCC_CFGR_SWS;
|
|
|
|
switch (tmp)
|
|
{
|
|
case 0x00: /* HSI used as system clock source */
|
|
RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
|
|
break;
|
|
case 0x04: /* HSE used as system clock source */
|
|
RCC_Clocks->SYSCLK_Frequency = HSE_VALUE;
|
|
break;
|
|
case 0x08: /* PLL used as system clock source */
|
|
|
|
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
|
|
SYSCLK = PLL_VCO / PLLP
|
|
*/
|
|
pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
|
|
pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
|
|
|
|
if (pllsource != 0)
|
|
{
|
|
/* HSE used as PLL clock source */
|
|
pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
|
|
}
|
|
else
|
|
{
|
|
/* HSI used as PLL clock source */
|
|
pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
|
|
}
|
|
|
|
pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
|
|
RCC_Clocks->SYSCLK_Frequency = pllvco/pllp;
|
|
break;
|
|
default:
|
|
RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
|
|
break;
|
|
}
|
|
/* Compute HCLK, PCLK1 and PCLK2 clocks frequencies ------------------------*/
|
|
|
|
/* Get HCLK prescaler */
|
|
tmp = RCC->CFGR & RCC_CFGR_HPRE;
|
|
tmp = tmp >> 4;
|
|
presc = APBAHBPrescTable[tmp];
|
|
/* HCLK clock frequency */
|
|
RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;
|
|
|
|
/* Get PCLK1 prescaler */
|
|
tmp = RCC->CFGR & RCC_CFGR_PPRE1;
|
|
tmp = tmp >> 10;
|
|
presc = APBAHBPrescTable[tmp];
|
|
/* PCLK1 clock frequency */
|
|
RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
|
|
|
|
/* Get PCLK2 prescaler */
|
|
tmp = RCC->CFGR & RCC_CFGR_PPRE2;
|
|
tmp = tmp >> 13;
|
|
presc = APBAHBPrescTable[tmp];
|
|
/* PCLK2 clock frequency */
|
|
RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
|
|
}
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup RCC_Group3 Peripheral clocks configuration functions
|
|
* @brief Peripheral clocks configuration functions
|
|
*
|
|
@verbatim
|
|
===============================================================================
|
|
##### Peripheral clocks configuration functions #####
|
|
===============================================================================
|
|
[..] This section provide functions allowing to configure the Peripheral clocks.
|
|
|
|
(#) The RTC clock which is derived from the LSI, LSE or HSE clock divided
|
|
by 2 to 31.
|
|
|
|
(#) After restart from Reset or wakeup from STANDBY, all peripherals are off
|
|
except internal SRAM, Flash and JTAG. Before to start using a peripheral
|
|
you have to enable its interface clock. You can do this using
|
|
RCC_AHBPeriphClockCmd(), RCC_APB2PeriphClockCmd() and RCC_APB1PeriphClockCmd() functions.
|
|
|
|
(#) To reset the peripherals configuration (to the default state after device reset)
|
|
you can use RCC_AHBPeriphResetCmd(), RCC_APB2PeriphResetCmd() and
|
|
RCC_APB1PeriphResetCmd() functions.
|
|
|
|
(#) To further reduce power consumption in SLEEP mode the peripheral clocks
|
|
can be disabled prior to executing the WFI or WFE instructions.
|
|
You can do this using RCC_AHBPeriphClockLPModeCmd(),
|
|
RCC_APB2PeriphClockLPModeCmd() and RCC_APB1PeriphClockLPModeCmd() functions.
|
|
|
|
@endverbatim
|
|
* @{
|
|
*/
|
|
|
|
/**
|
|
* @brief Configures the RTC clock (RTCCLK).
|
|
* @note As the RTC clock configuration bits are in the Backup domain and write
|
|
* access is denied to this domain after reset, you have to enable write
|
|
* access using PWR_BackupAccessCmd(ENABLE) function before to configure
|
|
* the RTC clock source (to be done once after reset).
|
|
* @note Once the RTC clock is configured it can't be changed unless the
|
|
* Backup domain is reset using RCC_BackupResetCmd() function, or by
|
|
* a Power On Reset (POR).
|
|
*
|
|
* @param RCC_RTCCLKSource: specifies the RTC clock source.
|
|
* This parameter can be one of the following values:
|
|
* @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock
|
|
* @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock
|
|
* @arg RCC_RTCCLKSource_HSE_Divx: HSE clock divided by x selected
|
|
* as RTC clock, where x:[2,31]
|
|
*
|
|
* @note If the LSE or LSI is used as RTC clock source, the RTC continues to
|
|
* work in STOP and STANDBY modes, and can be used as wakeup source.
|
|
* However, when the HSE clock is used as RTC clock source, the RTC
|
|
* cannot be used in STOP and STANDBY modes.
|
|
* @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
|
|
* RTC clock source).
|
|
*
|
|
* @retval None
|
|
*/
|
|
void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource)
|
|
{
|
|
uint32_t tmpreg = 0;
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource));
|
|
|
|
if ((RCC_RTCCLKSource & 0x00000300) == 0x00000300)
|
|
{ /* If HSE is selected as RTC clock source, configure HSE division factor for RTC clock */
|
|
tmpreg = RCC->CFGR;
|
|
|
|
/* Clear RTCPRE[4:0] bits */
|
|
tmpreg &= ~RCC_CFGR_RTCPRE;
|
|
|
|
/* Configure HSE division factor for RTC clock */
|
|
tmpreg |= (RCC_RTCCLKSource & 0xFFFFCFF);
|
|
|
|
/* Store the new value */
|
|
RCC->CFGR = tmpreg;
|
|
}
|
|
|
|
/* Select the RTC clock source */
|
|
RCC->BDCR |= (RCC_RTCCLKSource & 0x00000FFF);
|
|
}
|
|
|
|
/**
|
|
* @brief Enables or disables the RTC clock.
|
|
* @note This function must be used only after the RTC clock source was selected
|
|
* using the RCC_RTCCLKConfig function.
|
|
* @param NewState: new state of the RTC clock. This parameter can be: ENABLE or DISABLE.
|
|
* @retval None
|
|
*/
|
|
void RCC_RTCCLKCmd(FunctionalState NewState)
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
|
|
|
*(__IO uint32_t *) BDCR_RTCEN_BB = (uint32_t)NewState;
|
|
}
|
|
|
|
/**
|
|
* @brief Forces or releases the Backup domain reset.
|
|
* @note This function resets the RTC peripheral (including the backup registers)
|
|
* and the RTC clock source selection in RCC_CSR register.
|
|
* @note The BKPSRAM is not affected by this reset.
|
|
* @param NewState: new state of the Backup domain reset.
|
|
* This parameter can be: ENABLE or DISABLE.
|
|
* @retval None
|
|
*/
|
|
void RCC_BackupResetCmd(FunctionalState NewState)
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
|
*(__IO uint32_t *) BDCR_BDRST_BB = (uint32_t)NewState;
|
|
}
|
|
|
|
/**
|
|
* @brief Configures the I2S clock source (I2SCLK).
|
|
* @note This function must be called before enabling the I2S APB clock.
|
|
* @param RCC_I2SCLKSource: specifies the I2S clock source.
|
|
* This parameter can be one of the following values:
|
|
* @arg RCC_I2S2CLKSource_PLLI2S: PLLI2S clock used as I2S clock source
|
|
* @arg RCC_I2S2CLKSource_Ext: External clock mapped on the I2S_CKIN pin
|
|
* used as I2S clock source
|
|
* @retval None
|
|
*/
|
|
void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource)
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_I2SCLK_SOURCE(RCC_I2SCLKSource));
|
|
|
|
*(__IO uint32_t *) CFGR_I2SSRC_BB = RCC_I2SCLKSource;
|
|
}
|
|
|
|
/**
|
|
* @brief Configures the Timers clocks prescalers selection.
|
|
*
|
|
* @note This feature is only available with STM32F427x/437x Devices.
|
|
* @param RCC_TIMCLKPrescaler : specifies the Timers clocks prescalers selection
|
|
* This parameter can be one of the following values:
|
|
* @arg RCC_TIMPrescDesactivated: The Timers kernels clocks prescaler is
|
|
* equal to HPRE if PPREx is corresponding to division by 1 or 2,
|
|
* else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to
|
|
* division by 4 or more.
|
|
*
|
|
* @arg RCC_TIMPrescActivated: The Timers kernels clocks prescaler is
|
|
* equal to HPRE if PPREx is corresponding to division by 1, 2 or 4,
|
|
* else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding
|
|
* to division by 8 or more.
|
|
* @retval None
|
|
*/
|
|
void RCC_TIMCLKPresConfig(uint32_t RCC_TIMCLKPrescaler)
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_TIMCLK_PRESCALER(RCC_TIMCLKPrescaler));
|
|
|
|
*(__IO uint32_t *) DCKCFGR_TIMPRE_BB = RCC_TIMCLKPrescaler;
|
|
|
|
}
|
|
|
|
/**
|
|
* @brief Enables or disables the AHB1 peripheral clock.
|
|
* @note After reset, the peripheral clock (used for registers read/write access)
|
|
* is disabled and the application software has to enable this clock before
|
|
* using it.
|
|
* @param RCC_AHBPeriph: specifies the AHB1 peripheral to gates its clock.
|
|
* This parameter can be any combination of the following values:
|
|
* @arg RCC_AHB1Periph_GPIOA: GPIOA clock
|
|
* @arg RCC_AHB1Periph_GPIOB: GPIOB clock
|
|
* @arg RCC_AHB1Periph_GPIOC: GPIOC clock
|
|
* @arg RCC_AHB1Periph_GPIOD: GPIOD clock
|
|
* @arg RCC_AHB1Periph_GPIOE: GPIOE clock
|
|
* @arg RCC_AHB1Periph_GPIOF: GPIOF clock
|
|
* @arg RCC_AHB1Periph_GPIOG: GPIOG clock
|
|
* @arg RCC_AHB1Periph_GPIOG: GPIOG clock
|
|
* @arg RCC_AHB1Periph_GPIOI: GPIOI clock
|
|
* @arg RCC_AHB1Periph_CRC: CRC clock
|
|
* @arg RCC_AHB1Periph_BKPSRAM: BKPSRAM interface clock
|
|
* @arg RCC_AHB1Periph_CCMDATARAMEN CCM data RAM interface clock
|
|
* @arg RCC_AHB1Periph_DMA1: DMA1 clock
|
|
* @arg RCC_AHB1Periph_DMA2: DMA2 clock
|
|
* @arg RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock
|
|
* @arg RCC_AHB1Periph_ETH_MAC_Tx: Ethernet Transmission clock
|
|
* @arg RCC_AHB1Periph_ETH_MAC_Rx: Ethernet Reception clock
|
|
* @arg RCC_AHB1Periph_ETH_MAC_PTP: Ethernet PTP clock
|
|
* @arg RCC_AHB1Periph_OTG_HS: USB OTG HS clock
|
|
* @arg RCC_AHB1Periph_OTG_HS_ULPI: USB OTG HS ULPI clock
|
|
* @param NewState: new state of the specified peripheral clock.
|
|
* This parameter can be: ENABLE or DISABLE.
|
|
* @retval None
|
|
*/
|
|
void RCC_AHB1PeriphClockCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState)
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_AHB1_CLOCK_PERIPH(RCC_AHB1Periph));
|
|
|
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
|
if (NewState != DISABLE)
|
|
{
|
|
RCC->AHB1ENR |= RCC_AHB1Periph;
|
|
}
|
|
else
|
|
{
|
|
RCC->AHB1ENR &= ~RCC_AHB1Periph;
|
|
}
|
|
}
|
|
|
|
/**
|
|
* @brief Enables or disables the AHB2 peripheral clock.
|
|
* @note After reset, the peripheral clock (used for registers read/write access)
|
|
* is disabled and the application software has to enable this clock before
|
|
* using it.
|
|
* @param RCC_AHBPeriph: specifies the AHB2 peripheral to gates its clock.
|
|
* This parameter can be any combination of the following values:
|
|
* @arg RCC_AHB2Periph_DCMI: DCMI clock
|
|
* @arg RCC_AHB2Periph_CRYP: CRYP clock
|
|
* @arg RCC_AHB2Periph_HASH: HASH clock
|
|
* @arg RCC_AHB2Periph_RNG: RNG clock
|
|
* @arg RCC_AHB2Periph_OTG_FS: USB OTG FS clock
|
|
* @param NewState: new state of the specified peripheral clock.
|
|
* This parameter can be: ENABLE or DISABLE.
|
|
* @retval None
|
|
*/
|
|
void RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState)
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_AHB2_PERIPH(RCC_AHB2Periph));
|
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
|
|
|
if (NewState != DISABLE)
|
|
{
|
|
RCC->AHB2ENR |= RCC_AHB2Periph;
|
|
}
|
|
else
|
|
{
|
|
RCC->AHB2ENR &= ~RCC_AHB2Periph;
|
|
}
|
|
}
|
|
|
|
/**
|
|
* @brief Enables or disables the AHB3 peripheral clock.
|
|
* @note After reset, the peripheral clock (used for registers read/write access)
|
|
* is disabled and the application software has to enable this clock before
|
|
* using it.
|
|
* @param RCC_AHBPeriph: specifies the AHB3 peripheral to gates its clock.
|
|
* This parameter must be: RCC_AHB3Periph_FSMC
|
|
*
|
|
* @param NewState: new state of the specified peripheral clock.
|
|
* This parameter can be: ENABLE or DISABLE.
|
|
* @retval None
|
|
*/
|
|
void RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState)
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_AHB3_PERIPH(RCC_AHB3Periph));
|
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
|
|
|
if (NewState != DISABLE)
|
|
{
|
|
RCC->AHB3ENR |= RCC_AHB3Periph;
|
|
}
|
|
else
|
|
{
|
|
RCC->AHB3ENR &= ~RCC_AHB3Periph;
|
|
}
|
|
}
|
|
|
|
/**
|
|
* @brief Enables or disables the Low Speed APB (APB1) peripheral clock.
|
|
* @note After reset, the peripheral clock (used for registers read/write access)
|
|
* is disabled and the application software has to enable this clock before
|
|
* using it.
|
|
* @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock.
|
|
* This parameter can be any combination of the following values:
|
|
* @arg RCC_APB1Periph_TIM2: TIM2 clock
|
|
* @arg RCC_APB1Periph_TIM3: TIM3 clock
|
|
* @arg RCC_APB1Periph_TIM4: TIM4 clock
|
|
* @arg RCC_APB1Periph_TIM5: TIM5 clock
|
|
* @arg RCC_APB1Periph_TIM6: TIM6 clock
|
|
* @arg RCC_APB1Periph_TIM7: TIM7 clock
|
|
* @arg RCC_APB1Periph_TIM12: TIM12 clock
|
|
* @arg RCC_APB1Periph_TIM13: TIM13 clock
|
|
* @arg RCC_APB1Periph_TIM14: TIM14 clock
|
|
* @arg RCC_APB1Periph_WWDG: WWDG clock
|
|
* @arg RCC_APB1Periph_SPI2: SPI2 clock
|
|
* @arg RCC_APB1Periph_SPI3: SPI3 clock
|
|
* @arg RCC_APB1Periph_USART2: USART2 clock
|
|
* @arg RCC_APB1Periph_USART3: USART3 clock
|
|
* @arg RCC_APB1Periph_UART4: UART4 clock
|
|
* @arg RCC_APB1Periph_UART5: UART5 clock
|
|
* @arg RCC_APB1Periph_I2C1: I2C1 clock
|
|
* @arg RCC_APB1Periph_I2C2: I2C2 clock
|
|
* @arg RCC_APB1Periph_I2C3: I2C3 clock
|
|
* @arg RCC_APB1Periph_CAN1: CAN1 clock
|
|
* @arg RCC_APB1Periph_CAN2: CAN2 clock
|
|
* @arg RCC_APB1Periph_PWR: PWR clock
|
|
* @arg RCC_APB1Periph_DAC: DAC clock
|
|
* @arg RCC_APB1Periph_UART7: UART7 clock
|
|
* @arg RCC_APB1Periph_UART8: UART8 clock
|
|
* @param NewState: new state of the specified peripheral clock.
|
|
* This parameter can be: ENABLE or DISABLE.
|
|
* @retval None
|
|
*/
|
|
void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
|
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
|
|
|
if (NewState != DISABLE)
|
|
{
|
|
RCC->APB1ENR |= RCC_APB1Periph;
|
|
}
|
|
else
|
|
{
|
|
RCC->APB1ENR &= ~RCC_APB1Periph;
|
|
}
|
|
}
|
|
|
|
/**
|
|
* @brief Enables or disables the High Speed APB (APB2) peripheral clock.
|
|
* @note After reset, the peripheral clock (used for registers read/write access)
|
|
* is disabled and the application software has to enable this clock before
|
|
* using it.
|
|
* @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock.
|
|
* This parameter can be any combination of the following values:
|
|
* @arg RCC_APB2Periph_TIM1: TIM1 clock
|
|
* @arg RCC_APB2Periph_TIM8: TIM8 clock
|
|
* @arg RCC_APB2Periph_USART1: USART1 clock
|
|
* @arg RCC_APB2Periph_USART6: USART6 clock
|
|
* @arg RCC_APB2Periph_ADC1: ADC1 clock
|
|
* @arg RCC_APB2Periph_ADC2: ADC2 clock
|
|
* @arg RCC_APB2Periph_ADC3: ADC3 clock
|
|
* @arg RCC_APB2Periph_SDIO: SDIO clock
|
|
* @arg RCC_APB2Periph_SPI1: SPI1 clock
|
|
* @arg RCC_APB2Periph_SPI4: SPI4 clock
|
|
* @arg RCC_APB2Periph_SYSCFG: SYSCFG clock
|
|
* @arg RCC_APB2Periph_TIM9: TIM9 clock
|
|
* @arg RCC_APB2Periph_TIM10: TIM10 clock
|
|
* @arg RCC_APB2Periph_TIM11: TIM11 clock
|
|
* @arg RCC_APB2Periph_SPI5: SPI5 clock
|
|
* @arg RCC_APB2Periph_SPI6: SPI6 clock
|
|
* @param NewState: new state of the specified peripheral clock.
|
|
* This parameter can be: ENABLE or DISABLE.
|
|
* @retval None
|
|
*/
|
|
void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
|
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
|
|
|
if (NewState != DISABLE)
|
|
{
|
|
RCC->APB2ENR |= RCC_APB2Periph;
|
|
}
|
|
else
|
|
{
|
|
RCC->APB2ENR &= ~RCC_APB2Periph;
|
|
}
|
|
}
|
|
|
|
/**
|
|
* @brief Forces or releases AHB1 peripheral reset.
|
|
* @param RCC_AHB1Periph: specifies the AHB1 peripheral to reset.
|
|
* This parameter can be any combination of the following values:
|
|
* @arg RCC_AHB1Periph_GPIOA: GPIOA clock
|
|
* @arg RCC_AHB1Periph_GPIOB: GPIOB clock
|
|
* @arg RCC_AHB1Periph_GPIOC: GPIOC clock
|
|
* @arg RCC_AHB1Periph_GPIOD: GPIOD clock
|
|
* @arg RCC_AHB1Periph_GPIOE: GPIOE clock
|
|
* @arg RCC_AHB1Periph_GPIOF: GPIOF clock
|
|
* @arg RCC_AHB1Periph_GPIOG: GPIOG clock
|
|
* @arg RCC_AHB1Periph_GPIOG: GPIOG clock
|
|
* @arg RCC_AHB1Periph_GPIOI: GPIOI clock
|
|
* @arg RCC_AHB1Periph_CRC: CRC clock
|
|
* @arg RCC_AHB1Periph_DMA1: DMA1 clock
|
|
* @arg RCC_AHB1Periph_DMA2: DMA2 clock
|
|
* @arg RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock
|
|
* @arg RCC_AHB1Periph_OTG_HS: USB OTG HS clock
|
|
*
|
|
* @param NewState: new state of the specified peripheral reset.
|
|
* This parameter can be: ENABLE or DISABLE.
|
|
* @retval None
|
|
*/
|
|
void RCC_AHB1PeriphResetCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState)
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_AHB1_RESET_PERIPH(RCC_AHB1Periph));
|
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
|
|
|
if (NewState != DISABLE)
|
|
{
|
|
RCC->AHB1RSTR |= RCC_AHB1Periph;
|
|
}
|
|
else
|
|
{
|
|
RCC->AHB1RSTR &= ~RCC_AHB1Periph;
|
|
}
|
|
}
|
|
|
|
/**
|
|
* @brief Forces or releases AHB2 peripheral reset.
|
|
* @param RCC_AHB2Periph: specifies the AHB2 peripheral to reset.
|
|
* This parameter can be any combination of the following values:
|
|
* @arg RCC_AHB2Periph_DCMI: DCMI clock
|
|
* @arg RCC_AHB2Periph_CRYP: CRYP clock
|
|
* @arg RCC_AHB2Periph_HASH: HASH clock
|
|
* @arg RCC_AHB2Periph_RNG: RNG clock
|
|
* @arg RCC_AHB2Periph_OTG_FS: USB OTG FS clock
|
|
* @param NewState: new state of the specified peripheral reset.
|
|
* This parameter can be: ENABLE or DISABLE.
|
|
* @retval None
|
|
*/
|
|
void RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState)
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_AHB2_PERIPH(RCC_AHB2Periph));
|
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
|
|
|
if (NewState != DISABLE)
|
|
{
|
|
RCC->AHB2RSTR |= RCC_AHB2Periph;
|
|
}
|
|
else
|
|
{
|
|
RCC->AHB2RSTR &= ~RCC_AHB2Periph;
|
|
}
|
|
}
|
|
|
|
/**
|
|
* @brief Forces or releases AHB3 peripheral reset.
|
|
* @param RCC_AHB3Periph: specifies the AHB3 peripheral to reset.
|
|
* This parameter must be: RCC_AHB3Periph_FSMC
|
|
*
|
|
* @param NewState: new state of the specified peripheral reset.
|
|
* This parameter can be: ENABLE or DISABLE.
|
|
* @retval None
|
|
*/
|
|
void RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState)
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_AHB3_PERIPH(RCC_AHB3Periph));
|
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
|
|
|
if (NewState != DISABLE)
|
|
{
|
|
RCC->AHB3RSTR |= RCC_AHB3Periph;
|
|
}
|
|
else
|
|
{
|
|
RCC->AHB3RSTR &= ~RCC_AHB3Periph;
|
|
}
|
|
}
|
|
|
|
/**
|
|
* @brief Forces or releases Low Speed APB (APB1) peripheral reset.
|
|
* @param RCC_APB1Periph: specifies the APB1 peripheral to reset.
|
|
* This parameter can be any combination of the following values:
|
|
* @arg RCC_APB1Periph_TIM2: TIM2 clock
|
|
* @arg RCC_APB1Periph_TIM3: TIM3 clock
|
|
* @arg RCC_APB1Periph_TIM4: TIM4 clock
|
|
* @arg RCC_APB1Periph_TIM5: TIM5 clock
|
|
* @arg RCC_APB1Periph_TIM6: TIM6 clock
|
|
* @arg RCC_APB1Periph_TIM7: TIM7 clock
|
|
* @arg RCC_APB1Periph_TIM12: TIM12 clock
|
|
* @arg RCC_APB1Periph_TIM13: TIM13 clock
|
|
* @arg RCC_APB1Periph_TIM14: TIM14 clock
|
|
* @arg RCC_APB1Periph_WWDG: WWDG clock
|
|
* @arg RCC_APB1Periph_SPI2: SPI2 clock
|
|
* @arg RCC_APB1Periph_SPI3: SPI3 clock
|
|
* @arg RCC_APB1Periph_USART2: USART2 clock
|
|
* @arg RCC_APB1Periph_USART3: USART3 clock
|
|
* @arg RCC_APB1Periph_UART4: UART4 clock
|
|
* @arg RCC_APB1Periph_UART5: UART5 clock
|
|
* @arg RCC_APB1Periph_I2C1: I2C1 clock
|
|
* @arg RCC_APB1Periph_I2C2: I2C2 clock
|
|
* @arg RCC_APB1Periph_I2C3: I2C3 clock
|
|
* @arg RCC_APB1Periph_CAN1: CAN1 clock
|
|
* @arg RCC_APB1Periph_CAN2: CAN2 clock
|
|
* @arg RCC_APB1Periph_PWR: PWR clock
|
|
* @arg RCC_APB1Periph_DAC: DAC clock
|
|
* @arg RCC_APB1Periph_UART7: UART7 clock
|
|
* @arg RCC_APB1Periph_UART8: UART8 clock
|
|
* @param NewState: new state of the specified peripheral reset.
|
|
* This parameter can be: ENABLE or DISABLE.
|
|
* @retval None
|
|
*/
|
|
void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
|
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
|
if (NewState != DISABLE)
|
|
{
|
|
RCC->APB1RSTR |= RCC_APB1Periph;
|
|
}
|
|
else
|
|
{
|
|
RCC->APB1RSTR &= ~RCC_APB1Periph;
|
|
}
|
|
}
|
|
|
|
/**
|
|
* @brief Forces or releases High Speed APB (APB2) peripheral reset.
|
|
* @param RCC_APB2Periph: specifies the APB2 peripheral to reset.
|
|
* This parameter can be any combination of the following values:
|
|
* @arg RCC_APB2Periph_TIM1: TIM1 clock
|
|
* @arg RCC_APB2Periph_TIM8: TIM8 clock
|
|
* @arg RCC_APB2Periph_USART1: USART1 clock
|
|
* @arg RCC_APB2Periph_USART6: USART6 clock
|
|
* @arg RCC_APB2Periph_ADC1: ADC1 clock
|
|
* @arg RCC_APB2Periph_ADC2: ADC2 clock
|
|
* @arg RCC_APB2Periph_ADC3: ADC3 clock
|
|
* @arg RCC_APB2Periph_SDIO: SDIO clock
|
|
* @arg RCC_APB2Periph_SPI1: SPI1 clock
|
|
* @arg RCC_APB2Periph_SPI4: SPI4 clock
|
|
* @arg RCC_APB2Periph_SYSCFG: SYSCFG clock
|
|
* @arg RCC_APB2Periph_TIM9: TIM9 clock
|
|
* @arg RCC_APB2Periph_TIM10: TIM10 clock
|
|
* @arg RCC_APB2Periph_TIM11: TIM11 clock
|
|
* @arg RCC_APB2Periph_SPI5: SPI5 clock
|
|
* @arg RCC_APB2Periph_SPI6: SPI6 clock
|
|
* @param NewState: new state of the specified peripheral reset.
|
|
* This parameter can be: ENABLE or DISABLE.
|
|
* @retval None
|
|
*/
|
|
void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_APB2_RESET_PERIPH(RCC_APB2Periph));
|
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
|
if (NewState != DISABLE)
|
|
{
|
|
RCC->APB2RSTR |= RCC_APB2Periph;
|
|
}
|
|
else
|
|
{
|
|
RCC->APB2RSTR &= ~RCC_APB2Periph;
|
|
}
|
|
}
|
|
|
|
/**
|
|
* @brief Enables or disables the AHB1 peripheral clock during Low Power (Sleep) mode.
|
|
* @note Peripheral clock gating in SLEEP mode can be used to further reduce
|
|
* power consumption.
|
|
* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
|
|
* @note By default, all peripheral clocks are enabled during SLEEP mode.
|
|
* @param RCC_AHBPeriph: specifies the AHB1 peripheral to gates its clock.
|
|
* This parameter can be any combination of the following values:
|
|
* @arg RCC_AHB1Periph_GPIOA: GPIOA clock
|
|
* @arg RCC_AHB1Periph_GPIOB: GPIOB clock
|
|
* @arg RCC_AHB1Periph_GPIOC: GPIOC clock
|
|
* @arg RCC_AHB1Periph_GPIOD: GPIOD clock
|
|
* @arg RCC_AHB1Periph_GPIOE: GPIOE clock
|
|
* @arg RCC_AHB1Periph_GPIOF: GPIOF clock
|
|
* @arg RCC_AHB1Periph_GPIOG: GPIOG clock
|
|
* @arg RCC_AHB1Periph_GPIOG: GPIOG clock
|
|
* @arg RCC_AHB1Periph_GPIOI: GPIOI clock
|
|
* @arg RCC_AHB1Periph_CRC: CRC clock
|
|
* @arg RCC_AHB1Periph_BKPSRAM: BKPSRAM interface clock
|
|
* @arg RCC_AHB1Periph_DMA1: DMA1 clock
|
|
* @arg RCC_AHB1Periph_DMA2: DMA2 clock
|
|
* @arg RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock
|
|
* @arg RCC_AHB1Periph_ETH_MAC_Tx: Ethernet Transmission clock
|
|
* @arg RCC_AHB1Periph_ETH_MAC_Rx: Ethernet Reception clock
|
|
* @arg RCC_AHB1Periph_ETH_MAC_PTP: Ethernet PTP clock
|
|
* @arg RCC_AHB1Periph_OTG_HS: USB OTG HS clock
|
|
* @arg RCC_AHB1Periph_OTG_HS_ULPI: USB OTG HS ULPI clock
|
|
* @param NewState: new state of the specified peripheral clock.
|
|
* This parameter can be: ENABLE or DISABLE.
|
|
* @retval None
|
|
*/
|
|
void RCC_AHB1PeriphClockLPModeCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState)
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_AHB1_LPMODE_PERIPH(RCC_AHB1Periph));
|
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
|
if (NewState != DISABLE)
|
|
{
|
|
RCC->AHB1LPENR |= RCC_AHB1Periph;
|
|
}
|
|
else
|
|
{
|
|
RCC->AHB1LPENR &= ~RCC_AHB1Periph;
|
|
}
|
|
}
|
|
|
|
/**
|
|
* @brief Enables or disables the AHB2 peripheral clock during Low Power (Sleep) mode.
|
|
* @note Peripheral clock gating in SLEEP mode can be used to further reduce
|
|
* power consumption.
|
|
* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
|
|
* @note By default, all peripheral clocks are enabled during SLEEP mode.
|
|
* @param RCC_AHBPeriph: specifies the AHB2 peripheral to gates its clock.
|
|
* This parameter can be any combination of the following values:
|
|
* @arg RCC_AHB2Periph_DCMI: DCMI clock
|
|
* @arg RCC_AHB2Periph_CRYP: CRYP clock
|
|
* @arg RCC_AHB2Periph_HASH: HASH clock
|
|
* @arg RCC_AHB2Periph_RNG: RNG clock
|
|
* @arg RCC_AHB2Periph_OTG_FS: USB OTG FS clock
|
|
* @param NewState: new state of the specified peripheral clock.
|
|
* This parameter can be: ENABLE or DISABLE.
|
|
* @retval None
|
|
*/
|
|
void RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState)
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_AHB2_PERIPH(RCC_AHB2Periph));
|
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
|
if (NewState != DISABLE)
|
|
{
|
|
RCC->AHB2LPENR |= RCC_AHB2Periph;
|
|
}
|
|
else
|
|
{
|
|
RCC->AHB2LPENR &= ~RCC_AHB2Periph;
|
|
}
|
|
}
|
|
|
|
/**
|
|
* @brief Enables or disables the AHB3 peripheral clock during Low Power (Sleep) mode.
|
|
* @note Peripheral clock gating in SLEEP mode can be used to further reduce
|
|
* power consumption.
|
|
* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
|
|
* @note By default, all peripheral clocks are enabled during SLEEP mode.
|
|
* @param RCC_AHBPeriph: specifies the AHB3 peripheral to gates its clock.
|
|
* This parameter must be: RCC_AHB3Periph_FSMC
|
|
*
|
|
* @param NewState: new state of the specified peripheral clock.
|
|
* This parameter can be: ENABLE or DISABLE.
|
|
* @retval None
|
|
*/
|
|
void RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState)
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_AHB3_PERIPH(RCC_AHB3Periph));
|
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
|
if (NewState != DISABLE)
|
|
{
|
|
RCC->AHB3LPENR |= RCC_AHB3Periph;
|
|
}
|
|
else
|
|
{
|
|
RCC->AHB3LPENR &= ~RCC_AHB3Periph;
|
|
}
|
|
}
|
|
|
|
/**
|
|
* @brief Enables or disables the APB1 peripheral clock during Low Power (Sleep) mode.
|
|
* @note Peripheral clock gating in SLEEP mode can be used to further reduce
|
|
* power consumption.
|
|
* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
|
|
* @note By default, all peripheral clocks are enabled during SLEEP mode.
|
|
* @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock.
|
|
* This parameter can be any combination of the following values:
|
|
* @arg RCC_APB1Periph_TIM2: TIM2 clock
|
|
* @arg RCC_APB1Periph_TIM3: TIM3 clock
|
|
* @arg RCC_APB1Periph_TIM4: TIM4 clock
|
|
* @arg RCC_APB1Periph_TIM5: TIM5 clock
|
|
* @arg RCC_APB1Periph_TIM6: TIM6 clock
|
|
* @arg RCC_APB1Periph_TIM7: TIM7 clock
|
|
* @arg RCC_APB1Periph_TIM12: TIM12 clock
|
|
* @arg RCC_APB1Periph_TIM13: TIM13 clock
|
|
* @arg RCC_APB1Periph_TIM14: TIM14 clock
|
|
* @arg RCC_APB1Periph_WWDG: WWDG clock
|
|
* @arg RCC_APB1Periph_SPI2: SPI2 clock
|
|
* @arg RCC_APB1Periph_SPI3: SPI3 clock
|
|
* @arg RCC_APB1Periph_USART2: USART2 clock
|
|
* @arg RCC_APB1Periph_USART3: USART3 clock
|
|
* @arg RCC_APB1Periph_UART4: UART4 clock
|
|
* @arg RCC_APB1Periph_UART5: UART5 clock
|
|
* @arg RCC_APB1Periph_I2C1: I2C1 clock
|
|
* @arg RCC_APB1Periph_I2C2: I2C2 clock
|
|
* @arg RCC_APB1Periph_I2C3: I2C3 clock
|
|
* @arg RCC_APB1Periph_CAN1: CAN1 clock
|
|
* @arg RCC_APB1Periph_CAN2: CAN2 clock
|
|
* @arg RCC_APB1Periph_PWR: PWR clock
|
|
* @arg RCC_APB1Periph_DAC: DAC clock
|
|
* @arg RCC_APB1Periph_UART7: UART7 clock
|
|
* @arg RCC_APB1Periph_UART8: UART8 clock
|
|
* @param NewState: new state of the specified peripheral clock.
|
|
* This parameter can be: ENABLE or DISABLE.
|
|
* @retval None
|
|
*/
|
|
void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
|
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
|
if (NewState != DISABLE)
|
|
{
|
|
RCC->APB1LPENR |= RCC_APB1Periph;
|
|
}
|
|
else
|
|
{
|
|
RCC->APB1LPENR &= ~RCC_APB1Periph;
|
|
}
|
|
}
|
|
|
|
/**
|
|
* @brief Enables or disables the APB2 peripheral clock during Low Power (Sleep) mode.
|
|
* @note Peripheral clock gating in SLEEP mode can be used to further reduce
|
|
* power consumption.
|
|
* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
|
|
* @note By default, all peripheral clocks are enabled during SLEEP mode.
|
|
* @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock.
|
|
* This parameter can be any combination of the following values:
|
|
* @arg RCC_APB2Periph_TIM1: TIM1 clock
|
|
* @arg RCC_APB2Periph_TIM8: TIM8 clock
|
|
* @arg RCC_APB2Periph_USART1: USART1 clock
|
|
* @arg RCC_APB2Periph_USART6: USART6 clock
|
|
* @arg RCC_APB2Periph_ADC1: ADC1 clock
|
|
* @arg RCC_APB2Periph_ADC2: ADC2 clock
|
|
* @arg RCC_APB2Periph_ADC3: ADC3 clock
|
|
* @arg RCC_APB2Periph_SDIO: SDIO clock
|
|
* @arg RCC_APB2Periph_SPI1: SPI1 clock
|
|
* @arg RCC_APB2Periph_SPI4: SPI4 clock
|
|
* @arg RCC_APB2Periph_SYSCFG: SYSCFG clock
|
|
* @arg RCC_APB2Periph_TIM9: TIM9 clock
|
|
* @arg RCC_APB2Periph_TIM10: TIM10 clock
|
|
* @arg RCC_APB2Periph_TIM11: TIM11 clock
|
|
* @arg RCC_APB2Periph_SPI5: SPI5 clock
|
|
* @arg RCC_APB2Periph_SPI6: SPI6 clock
|
|
* @param NewState: new state of the specified peripheral clock.
|
|
* This parameter can be: ENABLE or DISABLE.
|
|
* @retval None
|
|
*/
|
|
void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
|
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
|
if (NewState != DISABLE)
|
|
{
|
|
RCC->APB2LPENR |= RCC_APB2Periph;
|
|
}
|
|
else
|
|
{
|
|
RCC->APB2LPENR &= ~RCC_APB2Periph;
|
|
}
|
|
}
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup RCC_Group4 Interrupts and flags management functions
|
|
* @brief Interrupts and flags management functions
|
|
*
|
|
@verbatim
|
|
===============================================================================
|
|
##### Interrupts and flags management functions #####
|
|
===============================================================================
|
|
|
|
@endverbatim
|
|
* @{
|
|
*/
|
|
|
|
/**
|
|
* @brief Enables or disables the specified RCC interrupts.
|
|
* @param RCC_IT: specifies the RCC interrupt sources to be enabled or disabled.
|
|
* This parameter can be any combination of the following values:
|
|
* @arg RCC_IT_LSIRDY: LSI ready interrupt
|
|
* @arg RCC_IT_LSERDY: LSE ready interrupt
|
|
* @arg RCC_IT_HSIRDY: HSI ready interrupt
|
|
* @arg RCC_IT_HSERDY: HSE ready interrupt
|
|
* @arg RCC_IT_PLLRDY: main PLL ready interrupt
|
|
* @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt
|
|
*
|
|
* @param NewState: new state of the specified RCC interrupts.
|
|
* This parameter can be: ENABLE or DISABLE.
|
|
* @retval None
|
|
*/
|
|
void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState)
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_IT(RCC_IT));
|
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
|
if (NewState != DISABLE)
|
|
{
|
|
/* Perform Byte access to RCC_CIR[14:8] bits to enable the selected interrupts */
|
|
*(__IO uint8_t *) CIR_BYTE2_ADDRESS |= RCC_IT;
|
|
}
|
|
else
|
|
{
|
|
/* Perform Byte access to RCC_CIR[14:8] bits to disable the selected interrupts */
|
|
*(__IO uint8_t *) CIR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT;
|
|
}
|
|
}
|
|
|
|
/**
|
|
* @brief Checks whether the specified RCC flag is set or not.
|
|
* @param RCC_FLAG: specifies the flag to check.
|
|
* This parameter can be one of the following values:
|
|
* @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
|
|
* @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
|
|
* @arg RCC_FLAG_PLLRDY: main PLL clock ready
|
|
* @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready
|
|
* @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
|
|
* @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
|
|
* @arg RCC_FLAG_BORRST: POR/PDR or BOR reset
|
|
* @arg RCC_FLAG_PINRST: Pin reset
|
|
* @arg RCC_FLAG_PORRST: POR/PDR reset
|
|
* @arg RCC_FLAG_SFTRST: Software reset
|
|
* @arg RCC_FLAG_IWDGRST: Independent Watchdog reset
|
|
* @arg RCC_FLAG_WWDGRST: Window Watchdog reset
|
|
* @arg RCC_FLAG_LPWRRST: Low Power reset
|
|
* @retval The new state of RCC_FLAG (SET or RESET).
|
|
*/
|
|
FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG)
|
|
{
|
|
uint32_t tmp = 0;
|
|
uint32_t statusreg = 0;
|
|
FlagStatus bitstatus = RESET;
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_FLAG(RCC_FLAG));
|
|
|
|
/* Get the RCC register index */
|
|
tmp = RCC_FLAG >> 5;
|
|
if (tmp == 1) /* The flag to check is in CR register */
|
|
{
|
|
statusreg = RCC->CR;
|
|
}
|
|
else if (tmp == 2) /* The flag to check is in BDCR register */
|
|
{
|
|
statusreg = RCC->BDCR;
|
|
}
|
|
else /* The flag to check is in CSR register */
|
|
{
|
|
statusreg = RCC->CSR;
|
|
}
|
|
|
|
/* Get the flag position */
|
|
tmp = RCC_FLAG & FLAG_MASK;
|
|
if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET)
|
|
{
|
|
bitstatus = SET;
|
|
}
|
|
else
|
|
{
|
|
bitstatus = RESET;
|
|
}
|
|
/* Return the flag status */
|
|
return bitstatus;
|
|
}
|
|
|
|
/**
|
|
* @brief Clears the RCC reset flags.
|
|
* The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,
|
|
* RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
void RCC_ClearFlag(void)
|
|
{
|
|
/* Set RMVF bit to clear the reset flags */
|
|
RCC->CSR |= RCC_CSR_RMVF;
|
|
}
|
|
|
|
/**
|
|
* @brief Checks whether the specified RCC interrupt has occurred or not.
|
|
* @param RCC_IT: specifies the RCC interrupt source to check.
|
|
* This parameter can be one of the following values:
|
|
* @arg RCC_IT_LSIRDY: LSI ready interrupt
|
|
* @arg RCC_IT_LSERDY: LSE ready interrupt
|
|
* @arg RCC_IT_HSIRDY: HSI ready interrupt
|
|
* @arg RCC_IT_HSERDY: HSE ready interrupt
|
|
* @arg RCC_IT_PLLRDY: main PLL ready interrupt
|
|
* @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt
|
|
* @arg RCC_IT_CSS: Clock Security System interrupt
|
|
* @retval The new state of RCC_IT (SET or RESET).
|
|
*/
|
|
ITStatus RCC_GetITStatus(uint8_t RCC_IT)
|
|
{
|
|
ITStatus bitstatus = RESET;
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_GET_IT(RCC_IT));
|
|
|
|
/* Check the status of the specified RCC interrupt */
|
|
if ((RCC->CIR & RCC_IT) != (uint32_t)RESET)
|
|
{
|
|
bitstatus = SET;
|
|
}
|
|
else
|
|
{
|
|
bitstatus = RESET;
|
|
}
|
|
/* Return the RCC_IT status */
|
|
return bitstatus;
|
|
}
|
|
|
|
/**
|
|
* @brief Clears the RCC's interrupt pending bits.
|
|
* @param RCC_IT: specifies the interrupt pending bit to clear.
|
|
* This parameter can be any combination of the following values:
|
|
* @arg RCC_IT_LSIRDY: LSI ready interrupt
|
|
* @arg RCC_IT_LSERDY: LSE ready interrupt
|
|
* @arg RCC_IT_HSIRDY: HSI ready interrupt
|
|
* @arg RCC_IT_HSERDY: HSE ready interrupt
|
|
* @arg RCC_IT_PLLRDY: main PLL ready interrupt
|
|
* @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt
|
|
* @arg RCC_IT_CSS: Clock Security System interrupt
|
|
* @retval None
|
|
*/
|
|
void RCC_ClearITPendingBit(uint8_t RCC_IT)
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_CLEAR_IT(RCC_IT));
|
|
|
|
/* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt
|
|
pending bits */
|
|
*(__IO uint8_t *) CIR_BYTE3_ADDRESS = RCC_IT;
|
|
}
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|