11657f2f20
To configure the SYSCLK on an F0 enable one of:
MICROPY_HW_CLK_USE_HSI48
MICROPY_HW_CLK_USE_HSE
MICROPY_HW_CLK_USE_BYPASS
232 lines
8.8 KiB
C
232 lines
8.8 KiB
C
/*
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* This file is part of the MicroPython project, http://micropython.org/
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*
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* Taken from ST Cube library and modified. See below for original header.
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*/
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/**
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******************************************************************************
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* @file system_stm32f0xx.c
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* @author MCD Application Team
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* @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File.
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*
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of STMicroelectronics nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************
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*/
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#include "py/mphal.h"
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#ifndef HSE_VALUE
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#define HSE_VALUE (8000000)
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#endif
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#ifndef HSI_VALUE
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#define HSI_VALUE (8000000)
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#endif
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#ifndef HSI48_VALUE
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#define HSI48_VALUE (48000000)
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#endif
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/* This variable is updated in three ways:
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1) by calling CMSIS function SystemCoreClockUpdate()
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2) by calling HAL API function HAL_RCC_GetHCLKFreq()
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3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
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Note: If you use this function to configure the system clock there is no need to
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call the 2 first functions listed above, since SystemCoreClock variable is
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updated automatically.
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*/
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uint32_t SystemCoreClock = 8000000;
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const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
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const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
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void SystemInit(void) {
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// Set HSION bit
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RCC->CR |= (uint32_t)0x00000001U;
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#if defined(STM32F051x8) || defined(STM32F058x8)
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// Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits
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RCC->CFGR &= (uint32_t)0xF8FFB80CU;
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#else
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// Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, MCOSEL[2:0], MCOPRE[2:0] and PLLNODIV bits
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RCC->CFGR &= (uint32_t)0x08FFB80CU;
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#endif
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// Reset HSEON, CSSON and PLLON bits
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RCC->CR &= (uint32_t)0xFEF6FFFFU;
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// Reset HSEBYP bit
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RCC->CR &= (uint32_t)0xFFFBFFFFU;
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// Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits
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RCC->CFGR &= (uint32_t)0xFFC0FFFFU;
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// Reset PREDIV[3:0] bits
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RCC->CFGR2 &= (uint32_t)0xFFFFFFF0U;
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#if defined(STM32F072xB) || defined(STM32F078xx)
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// Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits
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RCC->CFGR3 &= (uint32_t)0xFFFCFE2CU;
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#elif defined(STM32F071xB)
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// Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits
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RCC->CFGR3 &= (uint32_t)0xFFFFCEACU;
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#elif defined(STM32F091xC) || defined(STM32F098xx)
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// Reset USART3SW[1:0], USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits
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RCC->CFGR3 &= (uint32_t)0xFFF0FEACU;
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#elif defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx) || defined(STM32F030xC)
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// Reset USART1SW[1:0], I2C1SW and ADCSW bits
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RCC->CFGR3 &= (uint32_t)0xFFFFFEECU;
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#elif defined(STM32F051x8) || defined(STM32F058xx)
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// Reset USART1SW[1:0], I2C1SW, CECSW and ADCSW bits
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RCC->CFGR3 &= (uint32_t)0xFFFFFEACU;
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#elif defined(STM32F042x6) || defined(STM32F048xx)
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// Reset USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits
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RCC->CFGR3 &= (uint32_t)0xFFFFFE2CU;
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#elif defined(STM32F070x6) || defined(STM32F070xB)
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// Reset USART1SW[1:0], I2C1SW, USBSW and ADCSW bits
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RCC->CFGR3 &= (uint32_t)0xFFFFFE6CU;
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// Set default USB clock to PLLCLK, since there is no HSI48
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RCC->CFGR3 |= (uint32_t)0x00000080U;
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#else
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#warning "No target selected"
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#endif
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// Reset HSI14 bit
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RCC->CR2 &= (uint32_t)0xFFFFFFFEU;
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// Disable all interrupts
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RCC->CIR = 0x00000000U;
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// dpgeorge: enable 8-byte stack alignment for IRQ handlers, in accord with EABI
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SCB->CCR |= SCB_CCR_STKALIGN_Msk;
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}
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void SystemClock_Config(void) {
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// Enable power control peripheral
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__HAL_RCC_PWR_CLK_ENABLE();
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// Set flash latency to 1 because SYSCLK > 24MHz
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FLASH->ACR = (FLASH->ACR & ~0x7) | 0x1;
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#if MICROPY_HW_CLK_USE_HSI48
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// Use the 48MHz internal oscillator
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RCC->CR2 |= RCC_CR2_HSI48ON;
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while ((RCC->CR2 & RCC_CR2_HSI48RDY) == 0) {
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}
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const uint32_t sysclk_src = 3;
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#else
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// Use HSE and the PLL to get a 48MHz SYSCLK
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#if MICROPY_HW_CLK_USE_BYPASS
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RCC->CR |= RCC_CR_HSEBYP;
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#endif
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RCC->CR |= RCC_CR_HSEON;
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while ((RCC->CR & RCC_CR_HSERDY) == 0) {
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// Wait for HSE to be ready
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}
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RCC->CFGR = ((48000000 / HSE_VALUE) - 2) << RCC_CFGR_PLLMUL_Pos | 2 << RCC_CFGR_PLLSRC_Pos;
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RCC->CFGR2 = 0; // Input clock not divided
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RCC->CR |= RCC_CR_PLLON; // Turn PLL on
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while ((RCC->CR & RCC_CR_PLLRDY) == 0) {
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// Wait for PLL to lock
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}
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const uint32_t sysclk_src = 2;
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#endif
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// Select SYSCLK source
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RCC->CFGR |= sysclk_src << RCC_CFGR_SW_Pos;
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while (((RCC->CFGR >> RCC_CFGR_SWS_Pos) & 0x3) != sysclk_src) {
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// Wait for SYSCLK source to change
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}
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SystemCoreClockUpdate();
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HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq() / 1000);
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HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK);
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}
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void SystemCoreClockUpdate(void) {
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// Get SYSCLK source
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uint32_t tmp = RCC->CFGR & RCC_CFGR_SWS;
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switch (tmp) {
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case RCC_CFGR_SWS_HSI:
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SystemCoreClock = HSI_VALUE;
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break;
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case RCC_CFGR_SWS_HSE:
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SystemCoreClock = HSE_VALUE;
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break;
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case RCC_CFGR_SWS_PLL: {
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/* Get PLL clock source and multiplication factor */
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uint32_t pllmull = RCC->CFGR & RCC_CFGR_PLLMUL;
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uint32_t pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
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pllmull = (pllmull >> 18) + 2;
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uint32_t predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
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if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV) {
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/* HSE used as PLL clock source : SystemCoreClock = HSE/PREDIV * PLLMUL */
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SystemCoreClock = (HSE_VALUE/predivfactor) * pllmull;
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#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) \
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|| defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
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} else if (pllsource == RCC_CFGR_PLLSRC_HSI48_PREDIV) {
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/* HSI48 used as PLL clock source : SystemCoreClock = HSI48/PREDIV * PLLMUL */
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SystemCoreClock = (HSI48_VALUE/predivfactor) * pllmull;
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#endif
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} else {
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#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) \
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|| defined(STM32F078xx) || defined(STM32F071xB) || defined(STM32F072xB) \
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|| defined(STM32F070xB) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
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/* HSI used as PLL clock source : SystemCoreClock = HSI/PREDIV * PLLMUL */
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SystemCoreClock = (HSI_VALUE / predivfactor) * pllmull;
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#else
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/* HSI used as PLL clock source : SystemCoreClock = HSI/2 * PLLMUL */
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SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
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#endif
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}
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break;
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}
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case RCC_CFGR_SWS_HSI48:
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SystemCoreClock = HSI48_VALUE;
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break;
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default:
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SystemCoreClock = HSI_VALUE;
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break;
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}
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// Compute HCLK clock frequency
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tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
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SystemCoreClock >>= tmp;
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}
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/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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