102 lines
2.6 KiB
C
102 lines
2.6 KiB
C
#ifndef NRFX_CONFIG_H__
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#define NRFX_CONFIG_H__
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// Power
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#define NRFX_POWER_ENABLED 1
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#define NRFX_POWER_CONFIG_IRQ_PRIORITY 7
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// Turn on nrfx supported workarounds for errata in Rev1/Rev2 of nRF52832
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#ifdef NRF52832_XXAA
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#define NRFX_SPIS_NRF52_ANOMALY_109_WORKAROUND_ENABLED 1
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#endif
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// NOTE: THIS WORKAROUND CAUSES BLE CODE TO CRASH; tested on 2019-03-11.
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// Turn on nrfx supported workarounds for errata in Rev1 of nRF52840
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#ifdef NRF52840_XXAA
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// #define NRFX_SPIM3_NRF52840_ANOMALY_198_WORKAROUND_ENABLED 1
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#endif
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// SPI
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#define NRFX_SPIM_ENABLED 1
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// TWIM0 and TWIM1 are the same peripherals as SPIM0 and SPIM1.
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// The IRQ handlers for these peripherals are set up at compile time,
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// so out of the box TWIM0/SPIM0 and TWIM1/SPIM1 cannot be shared
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// between common-hal/busio/I2C.c and SPI.c.
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// We could write an interrupt handler that checks whether it's
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// being used for SPI or I2C, but perhaps two I2C's and 1-2 SPI's are good enough for now.
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// Enable SPIM1, SPIM2 and SPIM3 (if available)
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// No conflict with TWIM0.
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#define NRFX_SPIM1_ENABLED 1
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#define NRFX_SPIM2_ENABLED 1
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// DON'T ENABLE SPIM3 DUE TO ANOMALY WORKAROUND FAILURE (SEE ABOVE).
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// #ifdef NRF52840_XXAA
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// #define NRFX_SPIM_EXTENDED_ENABLED 1
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// #define NRFX_SPIM3_ENABLED 1
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// #else
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// #define NRFX_SPIM3_ENABLED 0
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// #endif
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#define NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY 7
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#define NRFX_SPIM_MISO_PULL_CFG 1
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// QSPI
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#define NRFX_QSPI_ENABLED 1
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// TWI aka. I2C; enable a single bus: TWIM0 (no conflict with SPIM1 and SPIM2)
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#define NRFX_TWIM_ENABLED 1
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#define NRFX_TWIM0_ENABLED 1
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//#define NRFX_TWIM1_ENABLED 1
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#define NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY 7
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#define NRFX_TWIM_DEFAULT_CONFIG_FREQUENCY NRF_TWIM_FREQ_400K
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#define NRFX_TWIM_DEFAULT_CONFIG_HOLD_BUS_UNINIT 0
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// UART
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#define NRFX_UARTE_ENABLED 1
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#define NRFX_UARTE0_ENABLED 1
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#define NRFX_UARTE1_ENABLED 1
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// PWM
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#define NRFX_PWM0_ENABLED 1
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#define NRFX_PWM1_ENABLED 1
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#define NRFX_PWM2_ENABLED 1
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#ifdef NRF_PWM3
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#define NRFX_PWM3_ENABLED 1
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#else
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#define NRFX_PWM3_ENABLED 0
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#endif
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#define NRFX_RTC_ENABLED 1
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#define NRFX_RTC0_ENABLED 1
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// TIMERS
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#define NRFX_TIMER_ENABLED 1
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// Don't enable TIMER0: it's used by the SoftDevice.
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#define NRFX_TIMER1_ENABLED 1
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#define NRFX_TIMER2_ENABLED 1
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#ifdef NRFX_TIMER3
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#define NRFX_TIMER3_ENABLED 1
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#else
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#define NRFX_TIMER3_ENABLED 0
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#endif
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#ifdef NRFX_TIMER4
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#define NRFX_TIMER4_ENABLED 1
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#else
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#define NRFX_TIMER4_ENABLED 0
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#endif
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#define NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY 7
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// GPIO interrupt
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#define NRFX_GPIOTE_ENABLED 1
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#define NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS 1
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#define NRFX_GPIOTE_CONFIG_IRQ_PRIORITY 7
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#endif // NRFX_CONFIG_H__
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