419 lines
15 KiB
C
419 lines
15 KiB
C
/*
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* This file is part of the MicroPython project, http://micropython.org/
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2018-2019 Damien P. George
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include <stdio.h>
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#include "py/mperrno.h"
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#include "py/mphal.h"
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#include "genhdr/pins.h"
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#include "pendsv.h"
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#include "sdio.h"
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#if MICROPY_PY_NETWORK_CYW43
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#define DEFAULT_MASK (0)
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enum {
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SDMMC_IRQ_STATE_DONE,
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SDMMC_IRQ_STATE_CMD_DONE,
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SDMMC_IRQ_STATE_CMD_DATA_PENDING,
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};
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static volatile int sdmmc_irq_state;
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static volatile uint32_t sdmmc_block_size_log2;
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static volatile bool sdmmc_write;
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static volatile bool sdmmc_dma;
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static volatile uint32_t sdmmc_error;
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static volatile uint8_t *sdmmc_buf_cur;
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static volatile uint8_t *sdmmc_buf_top;
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void sdio_init(uint32_t irq_pri) {
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// configure IO pins
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mp_hal_pin_config(pin_C8, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_UP, 12);
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mp_hal_pin_config(pin_C9, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_UP, 12);
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mp_hal_pin_config(pin_C10, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_UP, 12);
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mp_hal_pin_config(pin_C11, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_UP, 12);
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mp_hal_pin_config(pin_C12, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, 12); // CLK doesn't need pull-up
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mp_hal_pin_config(pin_D2, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_UP, 12);
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__HAL_RCC_SDMMC1_CLK_ENABLE(); // enable SDIO peripheral
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SDMMC_TypeDef *SDIO = SDMMC1;
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#if defined(STM32F7)
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SDIO->CLKCR = SDMMC_CLKCR_HWFC_EN | SDMMC_CLKCR_PWRSAV | (120 - 2); // 1-bit, 400kHz
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#else
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SDIO->CLKCR = SDMMC_CLKCR_HWFC_EN | SDMMC_CLKCR_PWRSAV | (120 / 2); // 1-bit, 400kHz
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#endif
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mp_hal_delay_us(10);
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SDIO->POWER = 3; // the card is clocked
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mp_hal_delay_us(10);
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SDIO->DCTRL = SDMMC_DCTRL_RWMOD; // RWMOD is SDIO_CK
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#if defined(STM32F7)
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SDIO->CLKCR |= SDMMC_CLKCR_CLKEN;
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#endif
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mp_hal_delay_us(10);
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__HAL_RCC_DMA2_CLK_ENABLE(); // enable DMA2 peripheral
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NVIC_SetPriority(SDMMC1_IRQn, irq_pri);
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SDIO->MASK = 0;
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HAL_NVIC_EnableIRQ(SDMMC1_IRQn);
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}
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void sdio_deinit(void) {
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__HAL_RCC_SDMMC1_CLK_DISABLE();
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#if defined(STM32F7)
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__HAL_RCC_DMA2_CLK_DISABLE();
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#endif
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}
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void sdio_enable_high_speed_4bit(void) {
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SDMMC_TypeDef *SDIO = SDMMC1;
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SDIO->POWER = 0; // power off
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mp_hal_delay_us(10);
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#if defined(STM32F7)
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SDIO->CLKCR = SDMMC_CLKCR_HWFC_EN | SDMMC_CLKCR_WIDBUS_0 | SDMMC_CLKCR_BYPASS /*| SDMMC_CLKCR_PWRSAV*/; // 4-bit, 48MHz
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#else
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SDIO->CLKCR = SDMMC_CLKCR_HWFC_EN | SDMMC_CLKCR_WIDBUS_0; // 4-bit, 48MHz
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#endif
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mp_hal_delay_us(10);
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SDIO->POWER = 3; // the card is clocked
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mp_hal_delay_us(10);
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SDIO->DCTRL = SDMMC_DCTRL_SDIOEN | SDMMC_DCTRL_RWMOD; // SDIOEN, RWMOD is SDIO_CK
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#if defined(STM32F7)
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SDIO->CLKCR |= SDMMC_CLKCR_CLKEN;
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#endif
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SDIO->MASK = DEFAULT_MASK;
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mp_hal_delay_us(10);
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}
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void SDMMC1_IRQHandler(void) {
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if (SDMMC1->STA & SDMMC_STA_CMDREND) {
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SDMMC1->ICR = SDMMC_ICR_CMDRENDC;
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uint32_t r1 = SDMMC1->RESP1;
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if (SDMMC1->RESPCMD == 53 && r1 & 0x800) {
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printf("bad RESP1: %lu %lx\n", SDMMC1->RESPCMD, r1);
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sdmmc_error = 0xffffffff;
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SDMMC1->MASK &= SDMMC_MASK_SDIOITIE;
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sdmmc_irq_state = SDMMC_IRQ_STATE_DONE;
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return;
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}
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#if defined(STM32H7)
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if (!sdmmc_dma) {
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while (sdmmc_buf_cur < sdmmc_buf_top && (SDMMC1->STA & SDMMC_STA_DPSMACT) && !(SDMMC1->STA & SDMMC_STA_RXFIFOE)) {
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*(uint32_t*)sdmmc_buf_cur = SDMMC1->FIFO;
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sdmmc_buf_cur += 4;
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}
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}
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#endif
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if (sdmmc_buf_cur >= sdmmc_buf_top) {
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// data transfer finished, so we are done
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SDMMC1->MASK &= SDMMC_MASK_SDIOITIE;
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sdmmc_irq_state = SDMMC_IRQ_STATE_DONE;
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return;
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}
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if (sdmmc_write) {
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SDMMC1->DCTRL =
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SDMMC_DCTRL_SDIOEN
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| SDMMC_DCTRL_RWMOD
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| sdmmc_block_size_log2 << SDMMC_DCTRL_DBLOCKSIZE_Pos
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#if defined(STM32F7)
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| (sdmmc_dma << SDMMC_DCTRL_DMAEN_Pos)
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#endif
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| (!sdmmc_write) << SDMMC_DCTRL_DTDIR_Pos
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| SDMMC_DCTRL_DTEN
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;
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if (!sdmmc_dma) {
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SDMMC1->MASK |= SDMMC_MASK_TXFIFOHEIE;
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}
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}
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sdmmc_irq_state = SDMMC_IRQ_STATE_CMD_DONE;
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} else if (SDMMC1->STA & SDMMC_STA_DATAEND) {
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// data transfer complete
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// note: it's possible to get DATAEND before CMDREND
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SDMMC1->ICR = SDMMC_ICR_DATAENDC;
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#if defined(STM32F7)
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// check if there is some remaining data in RXFIFO
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if (!sdmmc_dma) {
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while (SDMMC1->STA & SDMMC_STA_RXDAVL) {
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*(uint32_t*)sdmmc_buf_cur = SDMMC1->FIFO;
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sdmmc_buf_cur += 4;
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}
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}
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#endif
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if (sdmmc_irq_state == SDMMC_IRQ_STATE_CMD_DONE) {
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// command and data finished, so we are done
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SDMMC1->MASK &= SDMMC_MASK_SDIOITIE;
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sdmmc_irq_state = SDMMC_IRQ_STATE_DONE;
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}
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} else if (SDMMC1->STA & SDMMC_STA_TXFIFOHE) {
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if (!sdmmc_dma && sdmmc_write) {
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// write up to 8 words to fifo
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for (size_t i = 8; i && sdmmc_buf_cur < sdmmc_buf_top; --i) {
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SDMMC1->FIFO = *(uint32_t*)sdmmc_buf_cur;
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sdmmc_buf_cur += 4;
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}
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if (sdmmc_buf_cur >= sdmmc_buf_top) {
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// finished, disable IRQ
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SDMMC1->MASK &= ~SDMMC_MASK_TXFIFOHEIE;
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}
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}
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} else if (SDMMC1->STA & SDMMC_STA_RXFIFOHF) {
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if (!sdmmc_dma && !sdmmc_write) {
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// read up to 8 words from fifo
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for (size_t i = 8; i && sdmmc_buf_cur < sdmmc_buf_top; --i) {
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*(uint32_t*)sdmmc_buf_cur = SDMMC1->FIFO;
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sdmmc_buf_cur += 4;
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}
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}
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} else if (SDMMC1->STA & SDMMC_STA_SDIOIT) {
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SDMMC1->MASK &= ~SDMMC_MASK_SDIOITIE;
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SDMMC1->ICR = SDMMC_ICR_SDIOITC;
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#if MICROPY_PY_NETWORK_CYW43
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extern void (*cyw43_poll)(void);
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if (cyw43_poll) {
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pendsv_schedule_dispatch(PENDSV_DISPATCH_CYW43, cyw43_poll);
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}
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#endif
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} else if (SDMMC1->STA & 0x3f) {
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// an error
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sdmmc_error = SDMMC1->STA;
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SDMMC1->ICR = SDMMC_STATIC_FLAGS;
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SDMMC1->MASK &= SDMMC_MASK_SDIOITIE;
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sdmmc_irq_state = SDMMC_IRQ_STATE_DONE;
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}
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}
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int sdio_transfer(uint32_t cmd, uint32_t arg, uint32_t *resp) {
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#if defined(STM32F7)
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// Wait for any outstanding TX to complete
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while (SDMMC1->STA & SDMMC_STA_TXACT) {
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}
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#endif
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DMA2_Stream3->CR = 0; // ensure DMA is reset
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SDMMC1->ICR = SDMMC_STATIC_FLAGS; // clear interrupts
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SDMMC1->ARG = arg;
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SDMMC1->CMD = cmd | SDMMC_CMD_WAITRESP_0 | SDMMC_CMD_CPSMEN;
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sdmmc_irq_state = SDMMC_IRQ_STATE_CMD_DATA_PENDING;
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sdmmc_error = 0;
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sdmmc_buf_cur = NULL;
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sdmmc_buf_top = NULL;
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SDMMC1->MASK = (SDMMC1->MASK & SDMMC_MASK_SDIOITIE) | SDMMC_MASK_CMDRENDIE | 0x3f;
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uint32_t start = mp_hal_ticks_ms();
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for (;;) {
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__WFI();
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if (sdmmc_irq_state == SDMMC_IRQ_STATE_DONE) {
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break;
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}
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if (mp_hal_ticks_ms() - start > 1000) {
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SDMMC1->MASK = DEFAULT_MASK;
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printf("sdio_transfer timeout STA=0x%08x\n", (uint)SDMMC1->STA);
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return -MP_ETIMEDOUT;
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}
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}
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SDMMC1->MASK &= SDMMC_MASK_SDIOITIE;
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if (sdmmc_error == SDMMC_STA_CCRCFAIL && cmd == 5) {
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// Errata: CMD CRC error is incorrectly generated for CMD 5
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return 0;
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} else if (sdmmc_error) {
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return -(0x1000000 | sdmmc_error);
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}
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uint32_t rcmd = SDMMC1->RESPCMD;
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if (rcmd != cmd) {
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printf("sdio_transfer: cmd=%lu rcmd=%lu\n", cmd, rcmd);
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return -MP_EIO;
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}
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if (resp != NULL) {
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*resp = SDMMC1->RESP1;
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}
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return 0;
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}
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int sdio_transfer_cmd53(bool write, uint32_t block_size, uint32_t arg, size_t len, uint8_t *buf) {
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#if defined(STM32F7)
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// Wait for any outstanding TX to complete
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while (SDMMC1->STA & SDMMC_STA_TXACT) {
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}
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#endif
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// for SDIO_BYTE_MODE the SDIO chuck of data must be a single block of the length of buf
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int block_size_log2 = 0;
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if (block_size == 4) {
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block_size_log2 = 2;
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} else if (block_size == 8) {
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block_size_log2 = 3;
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} else if (block_size == 16) {
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block_size_log2 = 4;
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} else if (block_size == 32) {
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block_size_log2 = 5;
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} else if (block_size == 64) {
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block_size_log2 = 6;
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} else if (block_size == 128) {
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block_size_log2 = 7;
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} else if (block_size == 256) {
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block_size_log2 = 8;
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} else {
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printf("sdio_transfer_cmd53: invalid block_size %lu", block_size);
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return -MP_EINVAL;
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}
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bool dma = (len > 16);
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SDMMC1->ICR = SDMMC_STATIC_FLAGS; // clear interrupts
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SDMMC1->MASK &= SDMMC_MASK_SDIOITIE;
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SDMMC1->DTIMER = 0x2000000; // about 700ms running at 48MHz
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SDMMC1->DLEN = (len + block_size - 1) & ~(block_size - 1);
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DMA2_Stream3->CR = 0;
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if (dma) {
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// prepare DMA so it's ready when the DPSM starts its transfer
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#if defined(STM32F7)
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// enable DMA2 peripheral in case it was turned off by someone else
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RCC->AHB1ENR |= RCC_AHB1ENR_DMA2EN;
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#endif
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if (write) {
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// make sure cache is flushed to RAM so the DMA can read the correct data
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MP_HAL_CLEAN_DCACHE(buf, len);
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} else {
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// make sure cache is flushed and invalidated so when DMA updates the RAM
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// from reading the peripheral the CPU then reads the new data
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MP_HAL_CLEANINVALIDATE_DCACHE(buf, len);
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}
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#if defined(STM32F7)
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DMA2->LIFCR = 0x3f << 22;
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DMA2_Stream3->FCR = 0x07; // ?
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DMA2_Stream3->PAR = (uint32_t)&SDMMC1->FIFO;
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if ((uint32_t)buf & 3) {
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printf("sdio_transfer_cmd53: buf=%p is not aligned for DMA\n", buf);
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return -MP_EINVAL;
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}
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DMA2_Stream3->M0AR = (uint32_t)buf;
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DMA2_Stream3->NDTR = ((len + block_size - 1) & ~(block_size - 1)) / 4;
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DMA2_Stream3->CR = 4 << 25 // channel 4
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| 1 << 23 // MBURST INCR4
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| 1 << 21 // PBURST INCR4
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| 3 << 16 // PL very high
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| 2 << 13 // MSIZE word
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| 2 << 11 // PSIZE word
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| 1 << 10 // MINC enabled
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| 0 << 9 // PINC disabled
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| write << 6 // DIR mem-to-periph
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| 1 << 5 // PFCTRL periph is flow controller
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| 1 << 0 // EN
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;
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#else
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SDMMC1->IDMABASE0 = (uint32_t)buf;
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SDMMC1->IDMACTRL = SDMMC_IDMA_IDMAEN;
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#endif
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} else {
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#if defined(STM32H7)
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SDMMC1->IDMACTRL = 0;
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#endif
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}
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// for reading, need to initialise the DPSM before starting the CPSM
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// so that the DPSM is ready to receive when the device sends data
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// (and in case we get a long-running unrelated IRQ here on the host just
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// after writing to CMD to initiate the command)
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if (!write) {
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SDMMC1->DCTRL =
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SDMMC_DCTRL_SDIOEN
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| SDMMC_DCTRL_RWMOD
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| block_size_log2 << SDMMC_DCTRL_DBLOCKSIZE_Pos
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#if defined(STM32F7)
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| (dma << SDMMC_DCTRL_DMAEN_Pos)
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#endif
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| (!write) << SDMMC_DCTRL_DTDIR_Pos
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| SDMMC_DCTRL_DTEN
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;
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}
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SDMMC1->ARG = arg;
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SDMMC1->CMD = 53 | SDMMC_CMD_WAITRESP_0 | SDMMC_CMD_CPSMEN;
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sdmmc_irq_state = SDMMC_IRQ_STATE_CMD_DATA_PENDING;
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sdmmc_block_size_log2 = block_size_log2;
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sdmmc_write = write;
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sdmmc_dma = dma;
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sdmmc_error = 0;
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sdmmc_buf_cur = (uint8_t*)buf;
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sdmmc_buf_top = (uint8_t*)buf + len;
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SDMMC1->MASK = (SDMMC1->MASK & SDMMC_MASK_SDIOITIE) | SDMMC_MASK_CMDRENDIE | SDMMC_MASK_DATAENDIE | SDMMC_MASK_RXFIFOHFIE | 0x3f;
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// wait to complete transfer
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uint32_t start = mp_hal_ticks_ms();
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for (;;) {
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__WFI();
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if (sdmmc_irq_state == SDMMC_IRQ_STATE_DONE) {
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break;
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}
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if (mp_hal_ticks_ms() - start > 200) {
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SDMMC1->MASK &= SDMMC_MASK_SDIOITIE;
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#if defined(STM32F7)
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printf("sdio_transfer_cmd53: timeout wr=%d len=%u dma=%u buf_idx=%u STA=%08x SDMMC=%08x:%08x DMA=%08x:%08x:%08x RCC=%08x\n", write, (uint)len, (uint)dma, sdmmc_buf_cur - buf, (uint)SDMMC1->STA, (uint)SDMMC1->DCOUNT, (uint)SDMMC1->FIFOCNT, (uint)DMA2->LISR, (uint)DMA2->HISR, (uint)DMA2_Stream3->NDTR, (uint)RCC->AHB1ENR);
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#else
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printf("sdio_transfer_cmd53: timeout wr=%d len=%u dma=%u buf_idx=%u STA=%08x SDMMC=%08x:%08x IDMA=%08x\n", write, (uint)len, (uint)dma, sdmmc_buf_cur - buf, (uint)SDMMC1->STA, (uint)SDMMC1->DCOUNT, (uint)SDMMC1->DCTRL, (uint)SDMMC1->IDMACTRL);
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#endif
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return -MP_ETIMEDOUT;
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}
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}
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SDMMC1->MASK &= SDMMC_MASK_SDIOITIE;
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if (sdmmc_error) {
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#if defined(STM32F7)
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printf("sdio_transfer_cmd53: error=%08lx wr=%d len=%u dma=%u buf_idx=%u STA=%08x SDMMC=%08x:%08x DMA=%08x:%08x:%08x RCC=%08x\n", sdmmc_error, write, (uint)len, (uint)dma, sdmmc_buf_cur - buf, (uint)SDMMC1->STA, (uint)SDMMC1->DCOUNT, (uint)SDMMC1->FIFOCNT, (uint)DMA2->LISR, (uint)DMA2->HISR, (uint)DMA2_Stream3->NDTR, (uint)RCC->AHB1ENR);
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#else
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printf("sdio_transfer_cmd53: error=%08lx wr=%d len=%u dma=%u buf_idx=%u STA=%08x SDMMC=%08x:%08x IDMA=%08x\n", sdmmc_error, write, (uint)len, (uint)dma, sdmmc_buf_cur - buf, (uint)SDMMC1->STA, (uint)SDMMC1->DCOUNT, (uint)SDMMC1->DCTRL, (uint)SDMMC1->IDMACTRL);
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#endif
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return -(0x1000000 | sdmmc_error);
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}
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if (!sdmmc_dma) {
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if (sdmmc_buf_cur != sdmmc_buf_top) {
|
|
printf("sdio_transfer_cmd53: didn't transfer correct length: cur=%p top=%p\n", sdmmc_buf_cur, sdmmc_buf_top);
|
|
return -MP_EIO;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
#endif
|