circuitpython/ports/litex
2020-04-16 14:21:26 -07:00
..
boards ports: fomu: move more functions into ram for stability 2020-04-02 11:21:22 +08:00
common-hal Update copyright to bump the CI 2020-04-16 14:21:26 -07:00
hw ports: litex: add port and fomu board 2020-03-31 09:40:38 +08:00
supervisor ports: litex: add port and fomu board 2020-03-31 09:40:38 +08:00
background.c ports: litex: add port and fomu board 2020-03-31 09:40:38 +08:00
background.h ports: litex: add port and fomu board 2020-03-31 09:40:38 +08:00
crt0-vexriscv.S ports: litex: add port and fomu board 2020-03-31 09:40:38 +08:00
fatfs_port.c ports: litex: add port and fomu board 2020-03-31 09:40:38 +08:00
irq.h ports: litex: add port and fomu board 2020-03-31 09:40:38 +08:00
Makefile ports: litex: use dfu.py instead of dfu-suffix.py 2020-03-31 13:04:59 +08:00
mpconfigport.h litex: enable binascii and ujson modules 2020-04-16 10:02:08 +08:00
mpconfigport.mk litex: disable minimal build 2020-04-16 09:26:08 +08:00
mphalport.c litex: mphalport: add fake mp_hal_delay_us 2020-04-16 09:26:08 +08:00
mphalport.h ports: litex: add port and fomu board 2020-03-31 09:40:38 +08:00
qstrdefsport.h ports: litex: add port and fomu board 2020-03-31 09:40:38 +08:00
tick.c ports: litex: add port and fomu board 2020-03-31 09:40:38 +08:00
tick.h ports: litex: add port and fomu board 2020-03-31 09:40:38 +08:00