6839fff313
* atmel-samd: Remove ASF3. This will break builds. * atmel-samd: Add ASF4 for the SAMD21 and SAMD51. * Introduce the supervisor concept to facilitate porting. The supervisor is the code which runs individual MicroPython VMs. By splitting it out we make it more consistent and easier to find. This also adds very basic SAMD21 and SAMD51 support using the supervisor. Only the REPL currently works. This begins the work for #178.
109 lines
7.4 KiB
C
109 lines
7.4 KiB
C
/**
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* \file
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*
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* \brief Instance description for TC1
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*
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* Copyright (c) 2017 Atmel Corporation,
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* a wholly owned subsidiary of Microchip Technology Inc.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the Licence at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* \asf_license_stop
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*
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*/
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#ifndef _SAMD51_TC1_INSTANCE_
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#define _SAMD51_TC1_INSTANCE_
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/* ========== Register definition for TC1 peripheral ========== */
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#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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#define REG_TC1_CTRLA (0x40003C00) /**< \brief (TC1) Control A */
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#define REG_TC1_CTRLBCLR (0x40003C04) /**< \brief (TC1) Control B Clear */
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#define REG_TC1_CTRLBSET (0x40003C05) /**< \brief (TC1) Control B Set */
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#define REG_TC1_EVCTRL (0x40003C06) /**< \brief (TC1) Event Control */
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#define REG_TC1_INTENCLR (0x40003C08) /**< \brief (TC1) Interrupt Enable Clear */
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#define REG_TC1_INTENSET (0x40003C09) /**< \brief (TC1) Interrupt Enable Set */
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#define REG_TC1_INTFLAG (0x40003C0A) /**< \brief (TC1) Interrupt Flag Status and Clear */
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#define REG_TC1_STATUS (0x40003C0B) /**< \brief (TC1) Status */
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#define REG_TC1_WAVE (0x40003C0C) /**< \brief (TC1) Waveform Generation Control */
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#define REG_TC1_DRVCTRL (0x40003C0D) /**< \brief (TC1) Control C */
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#define REG_TC1_DBGCTRL (0x40003C0F) /**< \brief (TC1) Debug Control */
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#define REG_TC1_SYNCBUSY (0x40003C10) /**< \brief (TC1) Synchronization Status */
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#define REG_TC1_COUNT16_COUNT (0x40003C14) /**< \brief (TC1) COUNT16 Count */
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#define REG_TC1_COUNT16_CC0 (0x40003C1C) /**< \brief (TC1) COUNT16 Compare and Capture 0 */
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#define REG_TC1_COUNT16_CC1 (0x40003C1E) /**< \brief (TC1) COUNT16 Compare and Capture 1 */
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#define REG_TC1_COUNT16_CCBUF0 (0x40003C30) /**< \brief (TC1) COUNT16 Compare and Capture Buffer 0 */
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#define REG_TC1_COUNT16_CCBUF1 (0x40003C32) /**< \brief (TC1) COUNT16 Compare and Capture Buffer 1 */
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#define REG_TC1_COUNT32_COUNT (0x40003C14) /**< \brief (TC1) COUNT32 Count */
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#define REG_TC1_COUNT32_CC0 (0x40003C1C) /**< \brief (TC1) COUNT32 Compare and Capture 0 */
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#define REG_TC1_COUNT32_CC1 (0x40003C20) /**< \brief (TC1) COUNT32 Compare and Capture 1 */
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#define REG_TC1_COUNT32_CCBUF0 (0x40003C30) /**< \brief (TC1) COUNT32 Compare and Capture Buffer 0 */
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#define REG_TC1_COUNT32_CCBUF1 (0x40003C34) /**< \brief (TC1) COUNT32 Compare and Capture Buffer 1 */
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#define REG_TC1_COUNT8_COUNT (0x40003C14) /**< \brief (TC1) COUNT8 Count */
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#define REG_TC1_COUNT8_PER (0x40003C1B) /**< \brief (TC1) COUNT8 Period */
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#define REG_TC1_COUNT8_CC0 (0x40003C1C) /**< \brief (TC1) COUNT8 Compare and Capture 0 */
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#define REG_TC1_COUNT8_CC1 (0x40003C1D) /**< \brief (TC1) COUNT8 Compare and Capture 1 */
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#define REG_TC1_COUNT8_PERBUF (0x40003C2F) /**< \brief (TC1) COUNT8 Period Buffer */
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#define REG_TC1_COUNT8_CCBUF0 (0x40003C30) /**< \brief (TC1) COUNT8 Compare and Capture Buffer 0 */
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#define REG_TC1_COUNT8_CCBUF1 (0x40003C31) /**< \brief (TC1) COUNT8 Compare and Capture Buffer 1 */
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#else
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#define REG_TC1_CTRLA (*(RwReg *)0x40003C00UL) /**< \brief (TC1) Control A */
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#define REG_TC1_CTRLBCLR (*(RwReg8 *)0x40003C04UL) /**< \brief (TC1) Control B Clear */
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#define REG_TC1_CTRLBSET (*(RwReg8 *)0x40003C05UL) /**< \brief (TC1) Control B Set */
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#define REG_TC1_EVCTRL (*(RwReg16*)0x40003C06UL) /**< \brief (TC1) Event Control */
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#define REG_TC1_INTENCLR (*(RwReg8 *)0x40003C08UL) /**< \brief (TC1) Interrupt Enable Clear */
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#define REG_TC1_INTENSET (*(RwReg8 *)0x40003C09UL) /**< \brief (TC1) Interrupt Enable Set */
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#define REG_TC1_INTFLAG (*(RwReg8 *)0x40003C0AUL) /**< \brief (TC1) Interrupt Flag Status and Clear */
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#define REG_TC1_STATUS (*(RwReg8 *)0x40003C0BUL) /**< \brief (TC1) Status */
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#define REG_TC1_WAVE (*(RwReg8 *)0x40003C0CUL) /**< \brief (TC1) Waveform Generation Control */
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#define REG_TC1_DRVCTRL (*(RwReg8 *)0x40003C0DUL) /**< \brief (TC1) Control C */
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#define REG_TC1_DBGCTRL (*(RwReg8 *)0x40003C0FUL) /**< \brief (TC1) Debug Control */
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#define REG_TC1_SYNCBUSY (*(RoReg *)0x40003C10UL) /**< \brief (TC1) Synchronization Status */
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#define REG_TC1_COUNT16_COUNT (*(RwReg16*)0x40003C14UL) /**< \brief (TC1) COUNT16 Count */
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#define REG_TC1_COUNT16_CC0 (*(RwReg16*)0x40003C1CUL) /**< \brief (TC1) COUNT16 Compare and Capture 0 */
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#define REG_TC1_COUNT16_CC1 (*(RwReg16*)0x40003C1EUL) /**< \brief (TC1) COUNT16 Compare and Capture 1 */
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#define REG_TC1_COUNT16_CCBUF0 (*(RwReg16*)0x40003C30UL) /**< \brief (TC1) COUNT16 Compare and Capture Buffer 0 */
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#define REG_TC1_COUNT16_CCBUF1 (*(RwReg16*)0x40003C32UL) /**< \brief (TC1) COUNT16 Compare and Capture Buffer 1 */
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#define REG_TC1_COUNT32_COUNT (*(RwReg *)0x40003C14UL) /**< \brief (TC1) COUNT32 Count */
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#define REG_TC1_COUNT32_CC0 (*(RwReg *)0x40003C1CUL) /**< \brief (TC1) COUNT32 Compare and Capture 0 */
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#define REG_TC1_COUNT32_CC1 (*(RwReg *)0x40003C20UL) /**< \brief (TC1) COUNT32 Compare and Capture 1 */
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#define REG_TC1_COUNT32_CCBUF0 (*(RwReg *)0x40003C30UL) /**< \brief (TC1) COUNT32 Compare and Capture Buffer 0 */
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#define REG_TC1_COUNT32_CCBUF1 (*(RwReg *)0x40003C34UL) /**< \brief (TC1) COUNT32 Compare and Capture Buffer 1 */
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#define REG_TC1_COUNT8_COUNT (*(RwReg8 *)0x40003C14UL) /**< \brief (TC1) COUNT8 Count */
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#define REG_TC1_COUNT8_PER (*(RwReg8 *)0x40003C1BUL) /**< \brief (TC1) COUNT8 Period */
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#define REG_TC1_COUNT8_CC0 (*(RwReg8 *)0x40003C1CUL) /**< \brief (TC1) COUNT8 Compare and Capture 0 */
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#define REG_TC1_COUNT8_CC1 (*(RwReg8 *)0x40003C1DUL) /**< \brief (TC1) COUNT8 Compare and Capture 1 */
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#define REG_TC1_COUNT8_PERBUF (*(RwReg8 *)0x40003C2FUL) /**< \brief (TC1) COUNT8 Period Buffer */
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#define REG_TC1_COUNT8_CCBUF0 (*(RwReg8 *)0x40003C30UL) /**< \brief (TC1) COUNT8 Compare and Capture Buffer 0 */
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#define REG_TC1_COUNT8_CCBUF1 (*(RwReg8 *)0x40003C31UL) /**< \brief (TC1) COUNT8 Compare and Capture Buffer 1 */
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#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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/* ========== Instance parameters for TC1 peripheral ========== */
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#define TC1_CC_NUM 2
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#define TC1_DMAC_ID_MC_0 48
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#define TC1_DMAC_ID_MC_1 49
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#define TC1_DMAC_ID_MC_LSB 48
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#define TC1_DMAC_ID_MC_MSB 49
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#define TC1_DMAC_ID_MC_SIZE 2
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#define TC1_DMAC_ID_OVF 47 // Indexes of DMA Overflow trigger
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#define TC1_EXT 0 // Coding of implemented extended features (keep 0 value)
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#define TC1_GCLK_ID 9 // Index of Generic Clock
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#define TC1_MASTER_SLAVE_MODE 2 // TC type 0 : NA, 1 : Master, 2 : Slave
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#define TC1_OW_NUM 2 // Number of Output Waveforms
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#endif /* _SAMD51_TC1_INSTANCE_ */
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