6839fff313
* atmel-samd: Remove ASF3. This will break builds. * atmel-samd: Add ASF4 for the SAMD21 and SAMD51. * Introduce the supervisor concept to facilitate porting. The supervisor is the code which runs individual MicroPython VMs. By splitting it out we make it more consistent and easier to find. This also adds very basic SAMD21 and SAMD51 support using the supervisor. Only the REPL currently works. This begins the work for #178.
80 lines
4.8 KiB
C
80 lines
4.8 KiB
C
/**
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* \file
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*
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* \brief Instance description for PDEC
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*
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* Copyright (c) 2017 Atmel Corporation,
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* a wholly owned subsidiary of Microchip Technology Inc.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the Licence at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* \asf_license_stop
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*
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*/
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#ifndef _SAMD51_PDEC_INSTANCE_
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#define _SAMD51_PDEC_INSTANCE_
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/* ========== Register definition for PDEC peripheral ========== */
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#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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#define REG_PDEC_CTRLA (0x42001C00) /**< \brief (PDEC) Control A */
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#define REG_PDEC_CTRLBCLR (0x42001C04) /**< \brief (PDEC) Control B Clear */
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#define REG_PDEC_CTRLBSET (0x42001C05) /**< \brief (PDEC) Control B Set */
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#define REG_PDEC_EVCTRL (0x42001C06) /**< \brief (PDEC) Event Control */
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#define REG_PDEC_INTENCLR (0x42001C08) /**< \brief (PDEC) Interrupt Enable Clear */
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#define REG_PDEC_INTENSET (0x42001C09) /**< \brief (PDEC) Interrupt Enable Set */
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#define REG_PDEC_INTFLAG (0x42001C0A) /**< \brief (PDEC) Interrupt Flag Status and Clear */
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#define REG_PDEC_STATUS (0x42001C0C) /**< \brief (PDEC) Status */
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#define REG_PDEC_DBGCTRL (0x42001C0F) /**< \brief (PDEC) Debug Control */
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#define REG_PDEC_SYNCBUSY (0x42001C10) /**< \brief (PDEC) Synchronization Status */
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#define REG_PDEC_PRESC (0x42001C14) /**< \brief (PDEC) Prescaler Value */
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#define REG_PDEC_FILTER (0x42001C15) /**< \brief (PDEC) Filter Value */
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#define REG_PDEC_PRESCBUF (0x42001C18) /**< \brief (PDEC) Prescaler Buffer Value */
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#define REG_PDEC_FILTERBUF (0x42001C19) /**< \brief (PDEC) Filter Buffer Value */
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#define REG_PDEC_COUNT (0x42001C1C) /**< \brief (PDEC) Counter Value */
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#define REG_PDEC_CC0 (0x42001C20) /**< \brief (PDEC) Channel 0 Compare Value */
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#define REG_PDEC_CC1 (0x42001C24) /**< \brief (PDEC) Channel 1 Compare Value */
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#define REG_PDEC_CCBUF0 (0x42001C30) /**< \brief (PDEC) Channel Compare Buffer Value 0 */
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#define REG_PDEC_CCBUF1 (0x42001C34) /**< \brief (PDEC) Channel Compare Buffer Value 1 */
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#else
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#define REG_PDEC_CTRLA (*(RwReg *)0x42001C00UL) /**< \brief (PDEC) Control A */
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#define REG_PDEC_CTRLBCLR (*(RwReg8 *)0x42001C04UL) /**< \brief (PDEC) Control B Clear */
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#define REG_PDEC_CTRLBSET (*(RwReg8 *)0x42001C05UL) /**< \brief (PDEC) Control B Set */
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#define REG_PDEC_EVCTRL (*(RwReg16*)0x42001C06UL) /**< \brief (PDEC) Event Control */
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#define REG_PDEC_INTENCLR (*(RwReg8 *)0x42001C08UL) /**< \brief (PDEC) Interrupt Enable Clear */
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#define REG_PDEC_INTENSET (*(RwReg8 *)0x42001C09UL) /**< \brief (PDEC) Interrupt Enable Set */
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#define REG_PDEC_INTFLAG (*(RwReg8 *)0x42001C0AUL) /**< \brief (PDEC) Interrupt Flag Status and Clear */
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#define REG_PDEC_STATUS (*(RwReg16*)0x42001C0CUL) /**< \brief (PDEC) Status */
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#define REG_PDEC_DBGCTRL (*(RwReg8 *)0x42001C0FUL) /**< \brief (PDEC) Debug Control */
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#define REG_PDEC_SYNCBUSY (*(RoReg *)0x42001C10UL) /**< \brief (PDEC) Synchronization Status */
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#define REG_PDEC_PRESC (*(RwReg8 *)0x42001C14UL) /**< \brief (PDEC) Prescaler Value */
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#define REG_PDEC_FILTER (*(RwReg8 *)0x42001C15UL) /**< \brief (PDEC) Filter Value */
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#define REG_PDEC_PRESCBUF (*(RwReg8 *)0x42001C18UL) /**< \brief (PDEC) Prescaler Buffer Value */
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#define REG_PDEC_FILTERBUF (*(RwReg8 *)0x42001C19UL) /**< \brief (PDEC) Filter Buffer Value */
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#define REG_PDEC_COUNT (*(RwReg *)0x42001C1CUL) /**< \brief (PDEC) Counter Value */
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#define REG_PDEC_CC0 (*(RwReg *)0x42001C20UL) /**< \brief (PDEC) Channel 0 Compare Value */
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#define REG_PDEC_CC1 (*(RwReg *)0x42001C24UL) /**< \brief (PDEC) Channel 1 Compare Value */
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#define REG_PDEC_CCBUF0 (*(RwReg *)0x42001C30UL) /**< \brief (PDEC) Channel Compare Buffer Value 0 */
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#define REG_PDEC_CCBUF1 (*(RwReg *)0x42001C34UL) /**< \brief (PDEC) Channel Compare Buffer Value 1 */
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#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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/* ========== Instance parameters for PDEC peripheral ========== */
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#define PDEC_CC_NUM 2 // Number of Compare Channels units
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#define PDEC_GCLK_ID 31
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#endif /* _SAMD51_PDEC_INSTANCE_ */
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