6839fff313
* atmel-samd: Remove ASF3. This will break builds. * atmel-samd: Add ASF4 for the SAMD21 and SAMD51. * Introduce the supervisor concept to facilitate porting. The supervisor is the code which runs individual MicroPython VMs. By splitting it out we make it more consistent and easier to find. This also adds very basic SAMD21 and SAMD51 support using the supervisor. Only the REPL currently works. This begins the work for #178.
58 lines
2.8 KiB
C
58 lines
2.8 KiB
C
/**
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* \file
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*
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* \brief Instance description for PCC
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*
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* Copyright (c) 2017 Atmel Corporation,
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* a wholly owned subsidiary of Microchip Technology Inc.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the Licence at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* \asf_license_stop
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*
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*/
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#ifndef _SAMD51_PCC_INSTANCE_
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#define _SAMD51_PCC_INSTANCE_
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/* ========== Register definition for PCC peripheral ========== */
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#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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#define REG_PCC_MR (0x43002C00) /**< \brief (PCC) Mode Register */
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#define REG_PCC_IER (0x43002C04) /**< \brief (PCC) Interrupt Enable Register */
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#define REG_PCC_IDR (0x43002C08) /**< \brief (PCC) Interrupt Disable Register */
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#define REG_PCC_IMR (0x43002C0C) /**< \brief (PCC) Interrupt Mask Register */
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#define REG_PCC_ISR (0x43002C10) /**< \brief (PCC) Interrupt Status Register */
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#define REG_PCC_RHR (0x43002C14) /**< \brief (PCC) Reception Holding Register */
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#define REG_PCC_WPMR (0x43002CE0) /**< \brief (PCC) Write Protection Mode Register */
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#define REG_PCC_WPSR (0x43002CE4) /**< \brief (PCC) Write Protection Status Register */
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#else
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#define REG_PCC_MR (*(RwReg *)0x43002C00UL) /**< \brief (PCC) Mode Register */
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#define REG_PCC_IER (*(WoReg *)0x43002C04UL) /**< \brief (PCC) Interrupt Enable Register */
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#define REG_PCC_IDR (*(WoReg *)0x43002C08UL) /**< \brief (PCC) Interrupt Disable Register */
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#define REG_PCC_IMR (*(RoReg *)0x43002C0CUL) /**< \brief (PCC) Interrupt Mask Register */
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#define REG_PCC_ISR (*(RoReg *)0x43002C10UL) /**< \brief (PCC) Interrupt Status Register */
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#define REG_PCC_RHR (*(RoReg *)0x43002C14UL) /**< \brief (PCC) Reception Holding Register */
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#define REG_PCC_WPMR (*(RwReg *)0x43002CE0UL) /**< \brief (PCC) Write Protection Mode Register */
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#define REG_PCC_WPSR (*(RoReg *)0x43002CE4UL) /**< \brief (PCC) Write Protection Status Register */
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#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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/* ========== Instance parameters for PCC peripheral ========== */
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#define PCC_DATA_SIZE 14
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#define PCC_DMAC_ID_RX 80
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#endif /* _SAMD51_PCC_INSTANCE_ */
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