6839fff313
* atmel-samd: Remove ASF3. This will break builds. * atmel-samd: Add ASF4 for the SAMD21 and SAMD51. * Introduce the supervisor concept to facilitate porting. The supervisor is the code which runs individual MicroPython VMs. By splitting it out we make it more consistent and easier to find. This also adds very basic SAMD21 and SAMD51 support using the supervisor. Only the REPL currently works. This begins the work for #178.
69 lines
4.2 KiB
C
69 lines
4.2 KiB
C
/**
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* \file
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*
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* \brief Instance description for PAC
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*
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* Copyright (c) 2017 Atmel Corporation,
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* a wholly owned subsidiary of Microchip Technology Inc.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the Licence at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* \asf_license_stop
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*
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*/
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#ifndef _SAMD51_PAC_INSTANCE_
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#define _SAMD51_PAC_INSTANCE_
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/* ========== Register definition for PAC peripheral ========== */
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#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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#define REG_PAC_WRCTRL (0x40000000) /**< \brief (PAC) Write control */
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#define REG_PAC_EVCTRL (0x40000004) /**< \brief (PAC) Event control */
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#define REG_PAC_INTENCLR (0x40000008) /**< \brief (PAC) Interrupt enable clear */
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#define REG_PAC_INTENSET (0x40000009) /**< \brief (PAC) Interrupt enable set */
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#define REG_PAC_INTFLAGAHB (0x40000010) /**< \brief (PAC) Bridge interrupt flag status */
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#define REG_PAC_INTFLAGA (0x40000014) /**< \brief (PAC) Peripheral interrupt flag status - Bridge A */
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#define REG_PAC_INTFLAGB (0x40000018) /**< \brief (PAC) Peripheral interrupt flag status - Bridge B */
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#define REG_PAC_INTFLAGC (0x4000001C) /**< \brief (PAC) Peripheral interrupt flag status - Bridge C */
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#define REG_PAC_INTFLAGD (0x40000020) /**< \brief (PAC) Peripheral interrupt flag status - Bridge D */
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#define REG_PAC_STATUSA (0x40000034) /**< \brief (PAC) Peripheral write protection status - Bridge A */
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#define REG_PAC_STATUSB (0x40000038) /**< \brief (PAC) Peripheral write protection status - Bridge B */
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#define REG_PAC_STATUSC (0x4000003C) /**< \brief (PAC) Peripheral write protection status - Bridge C */
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#define REG_PAC_STATUSD (0x40000040) /**< \brief (PAC) Peripheral write protection status - Bridge D */
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#else
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#define REG_PAC_WRCTRL (*(RwReg *)0x40000000UL) /**< \brief (PAC) Write control */
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#define REG_PAC_EVCTRL (*(RwReg8 *)0x40000004UL) /**< \brief (PAC) Event control */
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#define REG_PAC_INTENCLR (*(RwReg8 *)0x40000008UL) /**< \brief (PAC) Interrupt enable clear */
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#define REG_PAC_INTENSET (*(RwReg8 *)0x40000009UL) /**< \brief (PAC) Interrupt enable set */
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#define REG_PAC_INTFLAGAHB (*(RwReg *)0x40000010UL) /**< \brief (PAC) Bridge interrupt flag status */
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#define REG_PAC_INTFLAGA (*(RwReg *)0x40000014UL) /**< \brief (PAC) Peripheral interrupt flag status - Bridge A */
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#define REG_PAC_INTFLAGB (*(RwReg *)0x40000018UL) /**< \brief (PAC) Peripheral interrupt flag status - Bridge B */
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#define REG_PAC_INTFLAGC (*(RwReg *)0x4000001CUL) /**< \brief (PAC) Peripheral interrupt flag status - Bridge C */
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#define REG_PAC_INTFLAGD (*(RwReg *)0x40000020UL) /**< \brief (PAC) Peripheral interrupt flag status - Bridge D */
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#define REG_PAC_STATUSA (*(RoReg *)0x40000034UL) /**< \brief (PAC) Peripheral write protection status - Bridge A */
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#define REG_PAC_STATUSB (*(RoReg *)0x40000038UL) /**< \brief (PAC) Peripheral write protection status - Bridge B */
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#define REG_PAC_STATUSC (*(RoReg *)0x4000003CUL) /**< \brief (PAC) Peripheral write protection status - Bridge C */
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#define REG_PAC_STATUSD (*(RoReg *)0x40000040UL) /**< \brief (PAC) Peripheral write protection status - Bridge D */
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#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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/* ========== Instance parameters for PAC peripheral ========== */
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#define PAC_CLK_AHB_DOMAIN // Clock domain of AHB clock
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#define PAC_CLK_AHB_ID 12 // AHB clock index
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#define PAC_HPB_NUM 4 // Number of bridges AHB/APB
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#endif /* _SAMD51_PAC_INSTANCE_ */
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