6839fff313
* atmel-samd: Remove ASF3. This will break builds. * atmel-samd: Add ASF4 for the SAMD21 and SAMD51. * Introduce the supervisor concept to facilitate porting. The supervisor is the code which runs individual MicroPython VMs. By splitting it out we make it more consistent and easier to find. This also adds very basic SAMD21 and SAMD51 support using the supervisor. Only the REPL currently works. This begins the work for #178.
77 lines
4.6 KiB
C
77 lines
4.6 KiB
C
/**
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* \file
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*
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* \brief Instance description for ICM
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*
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* Copyright (c) 2017 Atmel Corporation,
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* a wholly owned subsidiary of Microchip Technology Inc.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the Licence at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* \asf_license_stop
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*
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*/
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#ifndef _SAMD51_ICM_INSTANCE_
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#define _SAMD51_ICM_INSTANCE_
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/* ========== Register definition for ICM peripheral ========== */
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#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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#define REG_ICM_CFG (0x42002C00) /**< \brief (ICM) Configuration */
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#define REG_ICM_CTRL (0x42002C04) /**< \brief (ICM) Control */
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#define REG_ICM_SR (0x42002C08) /**< \brief (ICM) Status */
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#define REG_ICM_IER (0x42002C10) /**< \brief (ICM) Interrupt Enable */
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#define REG_ICM_IDR (0x42002C14) /**< \brief (ICM) Interrupt Disable */
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#define REG_ICM_IMR (0x42002C18) /**< \brief (ICM) Interrupt Mask */
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#define REG_ICM_ISR (0x42002C1C) /**< \brief (ICM) Interrupt Status */
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#define REG_ICM_UASR (0x42002C20) /**< \brief (ICM) Undefined Access Status */
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#define REG_ICM_DSCR (0x42002C30) /**< \brief (ICM) Region Descriptor Area Start Address */
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#define REG_ICM_HASH (0x42002C34) /**< \brief (ICM) Region Hash Area Start Address */
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#define REG_ICM_UIHVAL0 (0x42002C38) /**< \brief (ICM) User Initial Hash Value 0 */
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#define REG_ICM_UIHVAL1 (0x42002C3C) /**< \brief (ICM) User Initial Hash Value 1 */
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#define REG_ICM_UIHVAL2 (0x42002C40) /**< \brief (ICM) User Initial Hash Value 2 */
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#define REG_ICM_UIHVAL3 (0x42002C44) /**< \brief (ICM) User Initial Hash Value 3 */
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#define REG_ICM_UIHVAL4 (0x42002C48) /**< \brief (ICM) User Initial Hash Value 4 */
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#define REG_ICM_UIHVAL5 (0x42002C4C) /**< \brief (ICM) User Initial Hash Value 5 */
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#define REG_ICM_UIHVAL6 (0x42002C50) /**< \brief (ICM) User Initial Hash Value 6 */
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#define REG_ICM_UIHVAL7 (0x42002C54) /**< \brief (ICM) User Initial Hash Value 7 */
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#else
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#define REG_ICM_CFG (*(RwReg *)0x42002C00UL) /**< \brief (ICM) Configuration */
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#define REG_ICM_CTRL (*(WoReg *)0x42002C04UL) /**< \brief (ICM) Control */
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#define REG_ICM_SR (*(RoReg *)0x42002C08UL) /**< \brief (ICM) Status */
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#define REG_ICM_IER (*(WoReg *)0x42002C10UL) /**< \brief (ICM) Interrupt Enable */
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#define REG_ICM_IDR (*(WoReg *)0x42002C14UL) /**< \brief (ICM) Interrupt Disable */
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#define REG_ICM_IMR (*(RoReg *)0x42002C18UL) /**< \brief (ICM) Interrupt Mask */
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#define REG_ICM_ISR (*(RoReg *)0x42002C1CUL) /**< \brief (ICM) Interrupt Status */
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#define REG_ICM_UASR (*(RoReg *)0x42002C20UL) /**< \brief (ICM) Undefined Access Status */
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#define REG_ICM_DSCR (*(RwReg *)0x42002C30UL) /**< \brief (ICM) Region Descriptor Area Start Address */
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#define REG_ICM_HASH (*(RwReg *)0x42002C34UL) /**< \brief (ICM) Region Hash Area Start Address */
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#define REG_ICM_UIHVAL0 (*(WoReg *)0x42002C38UL) /**< \brief (ICM) User Initial Hash Value 0 */
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#define REG_ICM_UIHVAL1 (*(WoReg *)0x42002C3CUL) /**< \brief (ICM) User Initial Hash Value 1 */
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#define REG_ICM_UIHVAL2 (*(WoReg *)0x42002C40UL) /**< \brief (ICM) User Initial Hash Value 2 */
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#define REG_ICM_UIHVAL3 (*(WoReg *)0x42002C44UL) /**< \brief (ICM) User Initial Hash Value 3 */
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#define REG_ICM_UIHVAL4 (*(WoReg *)0x42002C48UL) /**< \brief (ICM) User Initial Hash Value 4 */
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#define REG_ICM_UIHVAL5 (*(WoReg *)0x42002C4CUL) /**< \brief (ICM) User Initial Hash Value 5 */
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#define REG_ICM_UIHVAL6 (*(WoReg *)0x42002C50UL) /**< \brief (ICM) User Initial Hash Value 6 */
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#define REG_ICM_UIHVAL7 (*(WoReg *)0x42002C54UL) /**< \brief (ICM) User Initial Hash Value 7 */
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#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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/* ========== Instance parameters for ICM peripheral ========== */
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#define ICM_CLK_AHB_ID 19
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#endif /* _SAMD51_ICM_INSTANCE_ */
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