6839fff313
* atmel-samd: Remove ASF3. This will break builds. * atmel-samd: Add ASF4 for the SAMD21 and SAMD51. * Introduce the supervisor concept to facilitate porting. The supervisor is the code which runs individual MicroPython VMs. By splitting it out we make it more consistent and easier to find. This also adds very basic SAMD21 and SAMD51 support using the supervisor. Only the REPL currently works. This begins the work for #178.
73 lines
4.3 KiB
C
73 lines
4.3 KiB
C
/**
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* \file
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*
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* \brief Instance description for EIC
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*
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* Copyright (c) 2017 Atmel Corporation,
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* a wholly owned subsidiary of Microchip Technology Inc.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the Licence at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* \asf_license_stop
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*
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*/
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#ifndef _SAMD51_EIC_INSTANCE_
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#define _SAMD51_EIC_INSTANCE_
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/* ========== Register definition for EIC peripheral ========== */
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#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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#define REG_EIC_CTRLA (0x40002800) /**< \brief (EIC) Control A */
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#define REG_EIC_NMICTRL (0x40002801) /**< \brief (EIC) Non-Maskable Interrupt Control */
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#define REG_EIC_NMIFLAG (0x40002802) /**< \brief (EIC) Non-Maskable Interrupt Flag Status and Clear */
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#define REG_EIC_SYNCBUSY (0x40002804) /**< \brief (EIC) Synchronization Busy */
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#define REG_EIC_EVCTRL (0x40002808) /**< \brief (EIC) Event Control */
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#define REG_EIC_INTENCLR (0x4000280C) /**< \brief (EIC) Interrupt Enable Clear */
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#define REG_EIC_INTENSET (0x40002810) /**< \brief (EIC) Interrupt Enable Set */
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#define REG_EIC_INTFLAG (0x40002814) /**< \brief (EIC) Interrupt Flag Status and Clear */
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#define REG_EIC_ASYNCH (0x40002818) /**< \brief (EIC) External Interrupt Asynchronous Mode */
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#define REG_EIC_CONFIG0 (0x4000281C) /**< \brief (EIC) External Interrupt Sense Configuration 0 */
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#define REG_EIC_CONFIG1 (0x40002820) /**< \brief (EIC) External Interrupt Sense Configuration 1 */
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#define REG_EIC_DEBOUNCEN (0x40002830) /**< \brief (EIC) Debouncer Enable */
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#define REG_EIC_DPRESCALER (0x40002834) /**< \brief (EIC) Debouncer Prescaler */
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#define REG_EIC_PINSTATE (0x40002838) /**< \brief (EIC) Pin State */
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#else
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#define REG_EIC_CTRLA (*(RwReg8 *)0x40002800UL) /**< \brief (EIC) Control A */
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#define REG_EIC_NMICTRL (*(RwReg8 *)0x40002801UL) /**< \brief (EIC) Non-Maskable Interrupt Control */
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#define REG_EIC_NMIFLAG (*(RwReg16*)0x40002802UL) /**< \brief (EIC) Non-Maskable Interrupt Flag Status and Clear */
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#define REG_EIC_SYNCBUSY (*(RoReg *)0x40002804UL) /**< \brief (EIC) Synchronization Busy */
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#define REG_EIC_EVCTRL (*(RwReg *)0x40002808UL) /**< \brief (EIC) Event Control */
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#define REG_EIC_INTENCLR (*(RwReg *)0x4000280CUL) /**< \brief (EIC) Interrupt Enable Clear */
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#define REG_EIC_INTENSET (*(RwReg *)0x40002810UL) /**< \brief (EIC) Interrupt Enable Set */
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#define REG_EIC_INTFLAG (*(RwReg *)0x40002814UL) /**< \brief (EIC) Interrupt Flag Status and Clear */
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#define REG_EIC_ASYNCH (*(RwReg *)0x40002818UL) /**< \brief (EIC) External Interrupt Asynchronous Mode */
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#define REG_EIC_CONFIG0 (*(RwReg *)0x4000281CUL) /**< \brief (EIC) External Interrupt Sense Configuration 0 */
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#define REG_EIC_CONFIG1 (*(RwReg *)0x40002820UL) /**< \brief (EIC) External Interrupt Sense Configuration 1 */
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#define REG_EIC_DEBOUNCEN (*(RwReg *)0x40002830UL) /**< \brief (EIC) Debouncer Enable */
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#define REG_EIC_DPRESCALER (*(RwReg *)0x40002834UL) /**< \brief (EIC) Debouncer Prescaler */
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#define REG_EIC_PINSTATE (*(RoReg *)0x40002838UL) /**< \brief (EIC) Pin State */
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#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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/* ========== Instance parameters for EIC peripheral ========== */
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#define EIC_EXTINT_NUM 16 // Number of external interrupts
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#define EIC_GCLK_ID 4 // Generic Clock index
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#define EIC_NUMBER_OF_CONFIG_REGS 2 // Number of CONFIG registers
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#define EIC_NUMBER_OF_DPRESCALER_REGS 2 // Number of DPRESCALER pin groups
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#define EIC_NUMBER_OF_INTERRUPTS 16 // Number of external interrupts (obsolete)
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#endif /* _SAMD51_EIC_INSTANCE_ */
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