6839fff313
* atmel-samd: Remove ASF3. This will break builds. * atmel-samd: Add ASF4 for the SAMD21 and SAMD51. * Introduce the supervisor concept to facilitate porting. The supervisor is the code which runs individual MicroPython VMs. By splitting it out we make it more consistent and easier to find. This also adds very basic SAMD21 and SAMD51 support using the supervisor. Only the REPL currently works. This begins the work for #178.
152 lines
12 KiB
C
152 lines
12 KiB
C
/**
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* \file
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*
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* \brief Instance description for CAN1
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*
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* Copyright (c) 2014 Atmel Corporation. All rights reserved.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. The name of Atmel may not be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* 4. This software may only be redistributed and used in connection with an
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* Atmel microcontroller product.
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*
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* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* \asf_license_stop
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*
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*/
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#ifndef _SAMD51_CAN1_INSTANCE_
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#define _SAMD51_CAN1_INSTANCE_
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/* ========== Register definition for CAN1 peripheral ========== */
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#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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#define REG_CAN1_CREL (0x42003800U) /**< \brief (CAN1) Core Release */
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#define REG_CAN1_ENDN (0x42003804U) /**< \brief (CAN1) Endian */
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#define REG_CAN1_MRCFG (0x42003808U) /**< \brief (CAN1) Message RAM Configuration */
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#define REG_CAN1_DBTP (0x4200380CU) /**< \brief (CAN1) Fast Bit Timing and Prescaler */
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#define REG_CAN1_TEST (0x42003810U) /**< \brief (CAN1) Test */
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#define REG_CAN1_RWD (0x42003814U) /**< \brief (CAN1) RAM Watchdog */
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#define REG_CAN1_CCCR (0x42003818U) /**< \brief (CAN1) CC Control */
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#define REG_CAN1_NBTP (0x4200381CU) /**< \brief (CAN1) Nominal Bit Timing and Prescaler */
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#define REG_CAN1_TSCC (0x42003820U) /**< \brief (CAN1) Timestamp Counter Configuration */
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#define REG_CAN1_TSCV (0x42003824U) /**< \brief (CAN1) Timestamp Counter Value */
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#define REG_CAN1_TOCC (0x42003828U) /**< \brief (CAN1) Timeout Counter Configuration */
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#define REG_CAN1_TOCV (0x4200382CU) /**< \brief (CAN1) Timeout Counter Value */
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#define REG_CAN1_ECR (0x42003840U) /**< \brief (CAN1) Error Counter */
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#define REG_CAN1_PSR (0x42003844U) /**< \brief (CAN1) Protocol Status */
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#define REG_CAN1_TDCR (0x42003848U) /**< \brief (CAN1) Extended ID Filter Configuration */
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#define REG_CAN1_IR (0x42003850U) /**< \brief (CAN1) Interrupt */
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#define REG_CAN1_IE (0x42003854U) /**< \brief (CAN1) Interrupt Enable */
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#define REG_CAN1_ILS (0x42003858U) /**< \brief (CAN1) Interrupt Line Select */
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#define REG_CAN1_ILE (0x4200385CU) /**< \brief (CAN1) Interrupt Line Enable */
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#define REG_CAN1_GFC (0x42003880U) /**< \brief (CAN1) Global Filter Configuration */
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#define REG_CAN1_SIDFC (0x42003884U) /**< \brief (CAN1) Standard ID Filter Configuration */
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#define REG_CAN1_XIDFC (0x42003888U) /**< \brief (CAN1) Extended ID Filter Configuration */
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#define REG_CAN1_XIDAM (0x42003890U) /**< \brief (CAN1) Extended ID AND Mask */
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#define REG_CAN1_HPMS (0x42003894U) /**< \brief (CAN1) High Priority Message Status */
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#define REG_CAN1_NDAT1 (0x42003898U) /**< \brief (CAN1) New Data 1 */
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#define REG_CAN1_NDAT2 (0x4200389CU) /**< \brief (CAN1) New Data 2 */
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#define REG_CAN1_RXF0C (0x420038A0U) /**< \brief (CAN1) Rx FIFO 0 Configuration */
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#define REG_CAN1_RXF0S (0x420038A4U) /**< \brief (CAN1) Rx FIFO 0 Status */
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#define REG_CAN1_RXF0A (0x420038A8U) /**< \brief (CAN1) Rx FIFO 0 Acknowledge */
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#define REG_CAN1_RXBC (0x420038ACU) /**< \brief (CAN1) Rx Buffer Configuration */
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#define REG_CAN1_RXF1C (0x420038B0U) /**< \brief (CAN1) Rx FIFO 1 Configuration */
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#define REG_CAN1_RXF1S (0x420038B4U) /**< \brief (CAN1) Rx FIFO 1 Status */
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#define REG_CAN1_RXF1A (0x420038B8U) /**< \brief (CAN1) Rx FIFO 1 Acknowledge */
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#define REG_CAN1_RXESC (0x420038BCU) /**< \brief (CAN1) Rx Buffer / FIFO Element Size Configuration */
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#define REG_CAN1_TXBC (0x420038C0U) /**< \brief (CAN1) Tx Buffer Configuration */
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#define REG_CAN1_TXFQS (0x420038C4U) /**< \brief (CAN1) Tx FIFO / Queue Status */
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#define REG_CAN1_TXESC (0x420038C8U) /**< \brief (CAN1) Tx Buffer Element Size Configuration */
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#define REG_CAN1_TXBRP (0x420038CCU) /**< \brief (CAN1) Tx Buffer Request Pending */
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#define REG_CAN1_TXBAR (0x420038D0U) /**< \brief (CAN1) Tx Buffer Add Request */
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#define REG_CAN1_TXBCR (0x420038D4U) /**< \brief (CAN1) Tx Buffer Cancellation Request */
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#define REG_CAN1_TXBTO (0x420038D8U) /**< \brief (CAN1) Tx Buffer Transmission Occurred */
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#define REG_CAN1_TXBCF (0x420038DCU) /**< \brief (CAN1) Tx Buffer Cancellation Finished */
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#define REG_CAN1_TXBTIE (0x420038E0U) /**< \brief (CAN1) Tx Buffer Transmission Interrupt Enable */
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#define REG_CAN1_TXBCIE (0x420038E4U) /**< \brief (CAN1) Tx Buffer Cancellation Finished Interrupt Enable */
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#define REG_CAN1_TXEFC (0x420038F0U) /**< \brief (CAN1) Tx Event FIFO Configuration */
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#define REG_CAN1_TXEFS (0x420038F4U) /**< \brief (CAN1) Tx Event FIFO Status */
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#define REG_CAN1_TXEFA (0x420038F8U) /**< \brief (CAN1) Tx Event FIFO Acknowledge */
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#else
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#define REG_CAN1_CREL (*(RoReg *)0x42003800U) /**< \brief (CAN1) Core Release */
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#define REG_CAN1_ENDN (*(RoReg *)0x42003804U) /**< \brief (CAN1) Endian */
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#define REG_CAN1_MRCFG (*(RwReg *)0x42003808U) /**< \brief (CAN1) Message RAM Configuration */
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#define REG_CAN1_DBTP (*(RwReg *)0x4200380CU) /**< \brief (CAN1) Fast Bit Timing and Prescaler */
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#define REG_CAN1_TEST (*(RwReg *)0x42003810U) /**< \brief (CAN1) Test */
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#define REG_CAN1_RWD (*(RwReg *)0x42003814U) /**< \brief (CAN1) RAM Watchdog */
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#define REG_CAN1_CCCR (*(RwReg *)0x42003818U) /**< \brief (CAN1) CC Control */
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#define REG_CAN1_NBTP (*(RwReg *)0x4200381CU) /**< \brief (CAN1) Nominal Bit Timing and Prescaler */
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#define REG_CAN1_TSCC (*(RwReg *)0x42003820U) /**< \brief (CAN1) Timestamp Counter Configuration */
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#define REG_CAN1_TSCV (*(RoReg *)0x42003824U) /**< \brief (CAN1) Timestamp Counter Value */
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#define REG_CAN1_TOCC (*(RwReg *)0x42003828U) /**< \brief (CAN1) Timeout Counter Configuration */
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#define REG_CAN1_TOCV (*(RwReg *)0x4200382CU) /**< \brief (CAN1) Timeout Counter Value */
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#define REG_CAN1_ECR (*(RoReg *)0x42003840U) /**< \brief (CAN1) Error Counter */
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#define REG_CAN1_PSR (*(RoReg *)0x42003844U) /**< \brief (CAN1) Protocol Status */
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#define REG_CAN1_TDCR (*(RwReg *)0x42003848U) /**< \brief (CAN1) Extended ID Filter Configuration */
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#define REG_CAN1_IR (*(RwReg *)0x42003850U) /**< \brief (CAN1) Interrupt */
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#define REG_CAN1_IE (*(RwReg *)0x42003854U) /**< \brief (CAN1) Interrupt Enable */
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#define REG_CAN1_ILS (*(RwReg *)0x42003858U) /**< \brief (CAN1) Interrupt Line Select */
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#define REG_CAN1_ILE (*(RwReg *)0x4200385CU) /**< \brief (CAN1) Interrupt Line Enable */
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#define REG_CAN1_GFC (*(RwReg *)0x42003880U) /**< \brief (CAN1) Global Filter Configuration */
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#define REG_CAN1_SIDFC (*(RwReg *)0x42003884U) /**< \brief (CAN1) Standard ID Filter Configuration */
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#define REG_CAN1_XIDFC (*(RwReg *)0x42003888U) /**< \brief (CAN1) Extended ID Filter Configuration */
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#define REG_CAN1_XIDAM (*(RwReg *)0x42003890U) /**< \brief (CAN1) Extended ID AND Mask */
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#define REG_CAN1_HPMS (*(RoReg *)0x42003894U) /**< \brief (CAN1) High Priority Message Status */
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#define REG_CAN1_NDAT1 (*(RwReg *)0x42003898U) /**< \brief (CAN1) New Data 1 */
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#define REG_CAN1_NDAT2 (*(RwReg *)0x4200389CU) /**< \brief (CAN1) New Data 2 */
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#define REG_CAN1_RXF0C (*(RwReg *)0x420038A0U) /**< \brief (CAN1) Rx FIFO 0 Configuration */
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#define REG_CAN1_RXF0S (*(RoReg *)0x420038A4U) /**< \brief (CAN1) Rx FIFO 0 Status */
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#define REG_CAN1_RXF0A (*(RwReg *)0x420038A8U) /**< \brief (CAN1) Rx FIFO 0 Acknowledge */
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#define REG_CAN1_RXBC (*(RwReg *)0x420038ACU) /**< \brief (CAN1) Rx Buffer Configuration */
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#define REG_CAN1_RXF1C (*(RwReg *)0x420038B0U) /**< \brief (CAN1) Rx FIFO 1 Configuration */
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#define REG_CAN1_RXF1S (*(RoReg *)0x420038B4U) /**< \brief (CAN1) Rx FIFO 1 Status */
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#define REG_CAN1_RXF1A (*(RwReg *)0x420038B8U) /**< \brief (CAN1) Rx FIFO 1 Acknowledge */
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#define REG_CAN1_RXESC (*(RwReg *)0x420038BCU) /**< \brief (CAN1) Rx Buffer / FIFO Element Size Configuration */
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#define REG_CAN1_TXBC (*(RwReg *)0x420038C0U) /**< \brief (CAN1) Tx Buffer Configuration */
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#define REG_CAN1_TXFQS (*(RoReg *)0x420038C4U) /**< \brief (CAN1) Tx FIFO / Queue Status */
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#define REG_CAN1_TXESC (*(RwReg *)0x420038C8U) /**< \brief (CAN1) Tx Buffer Element Size Configuration */
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#define REG_CAN1_TXBRP (*(RoReg *)0x420038CCU) /**< \brief (CAN1) Tx Buffer Request Pending */
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#define REG_CAN1_TXBAR (*(RwReg *)0x420038D0U) /**< \brief (CAN1) Tx Buffer Add Request */
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#define REG_CAN1_TXBCR (*(RwReg *)0x420038D4U) /**< \brief (CAN1) Tx Buffer Cancellation Request */
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#define REG_CAN1_TXBTO (*(RoReg *)0x420038D8U) /**< \brief (CAN1) Tx Buffer Transmission Occurred */
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#define REG_CAN1_TXBCF (*(RoReg *)0x420038DCU) /**< \brief (CAN1) Tx Buffer Cancellation Finished */
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#define REG_CAN1_TXBTIE (*(RwReg *)0x420038E0U) /**< \brief (CAN1) Tx Buffer Transmission Interrupt Enable */
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#define REG_CAN1_TXBCIE (*(RwReg *)0x420038E4U) /**< \brief (CAN1) Tx Buffer Cancellation Finished Interrupt Enable */
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#define REG_CAN1_TXEFC (*(RwReg *)0x420038F0U) /**< \brief (CAN1) Tx Event FIFO Configuration */
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#define REG_CAN1_TXEFS (*(RoReg *)0x420038F4U) /**< \brief (CAN1) Tx Event FIFO Status */
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#define REG_CAN1_TXEFA (*(RwReg *)0x420038F8U) /**< \brief (CAN1) Tx Event FIFO Acknowledge */
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#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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/* ========== Instance parameters for CAN1 peripheral ========== */
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#define CAN1_CLK_AHB_ID 22 // Index of AHB clock
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#define CAN1_DMAC_ID_DEBUG 38 // DMA CAN Debug Req
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#define CAN1_GCLK_ID 36 // Index of Generic Clock
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#endif /* _SAMD51_CAN1_INSTANCE_ */
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