6839fff313
* atmel-samd: Remove ASF3. This will break builds. * atmel-samd: Add ASF4 for the SAMD21 and SAMD51. * Introduce the supervisor concept to facilitate porting. The supervisor is the code which runs individual MicroPython VMs. By splitting it out we make it more consistent and easier to find. This also adds very basic SAMD21 and SAMD51 support using the supervisor. Only the REPL currently works. This begins the work for #178.
105 lines
6.7 KiB
C
105 lines
6.7 KiB
C
/**
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* \file
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*
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* \brief Instance description for AES
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*
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* Copyright (c) 2017 Atmel Corporation,
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* a wholly owned subsidiary of Microchip Technology Inc.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the Licence at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* \asf_license_stop
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*
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*/
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#ifndef _SAMD51_AES_INSTANCE_
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#define _SAMD51_AES_INSTANCE_
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/* ========== Register definition for AES peripheral ========== */
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#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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#define REG_AES_CTRLA (0x42002400) /**< \brief (AES) Control A */
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#define REG_AES_CTRLB (0x42002404) /**< \brief (AES) Control B */
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#define REG_AES_INTENCLR (0x42002405) /**< \brief (AES) Interrupt Enable Clear */
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#define REG_AES_INTENSET (0x42002406) /**< \brief (AES) Interrupt Enable Set */
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#define REG_AES_INTFLAG (0x42002407) /**< \brief (AES) Interrupt Flag Status */
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#define REG_AES_DATABUFPTR (0x42002408) /**< \brief (AES) Data buffer pointer */
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#define REG_AES_DBGCTRL (0x42002409) /**< \brief (AES) Debug control */
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#define REG_AES_KEYWORD0 (0x4200240C) /**< \brief (AES) Keyword 0 */
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#define REG_AES_KEYWORD1 (0x42002410) /**< \brief (AES) Keyword 1 */
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#define REG_AES_KEYWORD2 (0x42002414) /**< \brief (AES) Keyword 2 */
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#define REG_AES_KEYWORD3 (0x42002418) /**< \brief (AES) Keyword 3 */
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#define REG_AES_KEYWORD4 (0x4200241C) /**< \brief (AES) Keyword 4 */
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#define REG_AES_KEYWORD5 (0x42002420) /**< \brief (AES) Keyword 5 */
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#define REG_AES_KEYWORD6 (0x42002424) /**< \brief (AES) Keyword 6 */
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#define REG_AES_KEYWORD7 (0x42002428) /**< \brief (AES) Keyword 7 */
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#define REG_AES_INDATA (0x42002438) /**< \brief (AES) Indata */
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#define REG_AES_INTVECTV0 (0x4200243C) /**< \brief (AES) Initialisation Vector 0 */
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#define REG_AES_INTVECTV1 (0x42002440) /**< \brief (AES) Initialisation Vector 1 */
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#define REG_AES_INTVECTV2 (0x42002444) /**< \brief (AES) Initialisation Vector 2 */
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#define REG_AES_INTVECTV3 (0x42002448) /**< \brief (AES) Initialisation Vector 3 */
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#define REG_AES_HASHKEY0 (0x4200245C) /**< \brief (AES) Hash key 0 */
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#define REG_AES_HASHKEY1 (0x42002460) /**< \brief (AES) Hash key 1 */
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#define REG_AES_HASHKEY2 (0x42002464) /**< \brief (AES) Hash key 2 */
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#define REG_AES_HASHKEY3 (0x42002468) /**< \brief (AES) Hash key 3 */
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#define REG_AES_GHASH0 (0x4200246C) /**< \brief (AES) Galois Hash 0 */
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#define REG_AES_GHASH1 (0x42002470) /**< \brief (AES) Galois Hash 1 */
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#define REG_AES_GHASH2 (0x42002474) /**< \brief (AES) Galois Hash 2 */
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#define REG_AES_GHASH3 (0x42002478) /**< \brief (AES) Galois Hash 3 */
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#define REG_AES_CIPLEN (0x42002480) /**< \brief (AES) Cipher Length */
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#define REG_AES_RANDSEED (0x42002484) /**< \brief (AES) Random Seed */
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#else
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#define REG_AES_CTRLA (*(RwReg *)0x42002400UL) /**< \brief (AES) Control A */
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#define REG_AES_CTRLB (*(RwReg8 *)0x42002404UL) /**< \brief (AES) Control B */
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#define REG_AES_INTENCLR (*(RwReg8 *)0x42002405UL) /**< \brief (AES) Interrupt Enable Clear */
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#define REG_AES_INTENSET (*(RwReg8 *)0x42002406UL) /**< \brief (AES) Interrupt Enable Set */
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#define REG_AES_INTFLAG (*(RwReg8 *)0x42002407UL) /**< \brief (AES) Interrupt Flag Status */
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#define REG_AES_DATABUFPTR (*(RwReg8 *)0x42002408UL) /**< \brief (AES) Data buffer pointer */
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#define REG_AES_DBGCTRL (*(RwReg8 *)0x42002409UL) /**< \brief (AES) Debug control */
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#define REG_AES_KEYWORD0 (*(WoReg *)0x4200240CUL) /**< \brief (AES) Keyword 0 */
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#define REG_AES_KEYWORD1 (*(WoReg *)0x42002410UL) /**< \brief (AES) Keyword 1 */
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#define REG_AES_KEYWORD2 (*(WoReg *)0x42002414UL) /**< \brief (AES) Keyword 2 */
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#define REG_AES_KEYWORD3 (*(WoReg *)0x42002418UL) /**< \brief (AES) Keyword 3 */
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#define REG_AES_KEYWORD4 (*(WoReg *)0x4200241CUL) /**< \brief (AES) Keyword 4 */
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#define REG_AES_KEYWORD5 (*(WoReg *)0x42002420UL) /**< \brief (AES) Keyword 5 */
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#define REG_AES_KEYWORD6 (*(WoReg *)0x42002424UL) /**< \brief (AES) Keyword 6 */
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#define REG_AES_KEYWORD7 (*(WoReg *)0x42002428UL) /**< \brief (AES) Keyword 7 */
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#define REG_AES_INDATA (*(RwReg *)0x42002438UL) /**< \brief (AES) Indata */
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#define REG_AES_INTVECTV0 (*(WoReg *)0x4200243CUL) /**< \brief (AES) Initialisation Vector 0 */
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#define REG_AES_INTVECTV1 (*(WoReg *)0x42002440UL) /**< \brief (AES) Initialisation Vector 1 */
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#define REG_AES_INTVECTV2 (*(WoReg *)0x42002444UL) /**< \brief (AES) Initialisation Vector 2 */
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#define REG_AES_INTVECTV3 (*(WoReg *)0x42002448UL) /**< \brief (AES) Initialisation Vector 3 */
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#define REG_AES_HASHKEY0 (*(RwReg *)0x4200245CUL) /**< \brief (AES) Hash key 0 */
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#define REG_AES_HASHKEY1 (*(RwReg *)0x42002460UL) /**< \brief (AES) Hash key 1 */
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#define REG_AES_HASHKEY2 (*(RwReg *)0x42002464UL) /**< \brief (AES) Hash key 2 */
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#define REG_AES_HASHKEY3 (*(RwReg *)0x42002468UL) /**< \brief (AES) Hash key 3 */
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#define REG_AES_GHASH0 (*(RwReg *)0x4200246CUL) /**< \brief (AES) Galois Hash 0 */
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#define REG_AES_GHASH1 (*(RwReg *)0x42002470UL) /**< \brief (AES) Galois Hash 1 */
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#define REG_AES_GHASH2 (*(RwReg *)0x42002474UL) /**< \brief (AES) Galois Hash 2 */
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#define REG_AES_GHASH3 (*(RwReg *)0x42002478UL) /**< \brief (AES) Galois Hash 3 */
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#define REG_AES_CIPLEN (*(RwReg *)0x42002480UL) /**< \brief (AES) Cipher Length */
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#define REG_AES_RANDSEED (*(RwReg *)0x42002484UL) /**< \brief (AES) Random Seed */
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#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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/* ========== Instance parameters for AES peripheral ========== */
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#define AES_DMAC_ID_RD 82 // DMA DATA Read trigger
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#define AES_DMAC_ID_WR 81 // DMA DATA Write trigger
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#define AES_FOUR_BYTE_OPERATION 1 // Byte Operation
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#define AES_GCM 1 // GCM
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#define AES_KEYLEN 2 // Key Length
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#endif /* _SAMD51_AES_INSTANCE_ */
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