2c8c2b935e
This commit improves pllvalues.py to generate PLL values for H7 MCUs that are valid (VCO in and out are in range) and extend for the entire range of SYSCLK values up to 400MHz (up to 480MHz is currently unsupported).
281 lines
9.2 KiB
Python
281 lines
9.2 KiB
Python
"""
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This is an auxiliary script that is used to compute valid PLL values to set
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the CPU frequency to a given value. The algorithm here appears as C code
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for the machine.freq() function.
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"""
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from __future__ import print_function
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import re
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class MCU:
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def __init__(self, range_sysclk, range_m, range_n, range_p, range_q, range_vco_in, range_vco_out):
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self.range_sysclk = range_sysclk
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self.range_m = range_m
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self.range_n = range_n
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self.range_p = range_p
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self.range_q = range_q
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self.range_vco_in = range_vco_in
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self.range_vco_out = range_vco_out
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mcu_default = MCU(
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range_sysclk=range(2, 216 + 1, 2),
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range_m=range(2, 63 + 1),
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range_n=range(192, 432 + 1),
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range_p=range(2, 8 + 1, 2),
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range_q=range(2, 15 + 1),
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range_vco_in=range(1, 2 + 1),
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range_vco_out=range(192, 432 + 1),
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)
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mcu_h7 = MCU(
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range_sysclk=range(2, 400 + 1, 2), # above 400MHz currently unsupported
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range_m=range(1, 63 + 1),
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range_n=range(4, 512 + 1),
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range_p=range(2, 128 + 1, 2),
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range_q=range(1, 128 + 1),
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range_vco_in=range(1, 16 + 1),
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range_vco_out=range(150, 960 + 1), # 150-420=medium, 192-960=wide
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)
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def close_int(x):
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return abs(x - round(x)) < 0.01
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# original version that requires N/M to be an integer (for simplicity)
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def compute_pll(hse, sys):
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for P in (2, 4, 6, 8): # allowed values of P
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Q = sys * P / 48
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NbyM = sys * P / hse
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# N/M and Q must be integers
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if not (close_int(NbyM) and close_int(Q)):
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continue
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# VCO_OUT must be between 192MHz and 432MHz
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if not (192 <= hse * NbyM <= 432):
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continue
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# compute M
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M = int(192 // NbyM)
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while hse > 2 * M or NbyM * M < 192:
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M += 1
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# VCO_IN must be between 1MHz and 2MHz (2MHz recommended)
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if not (M <= hse):
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continue
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# compute N
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N = NbyM * M
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# N and Q are restricted
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if not (192 <= N <= 432 and 2 <= Q <= 15):
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continue
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# found valid values
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assert NbyM == N // M
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return (M, N, P, Q)
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# no valid values found
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return None
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# improved version that doesn't require N/M to be an integer
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def compute_pll2(hse, sys, relax_pll48):
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# Loop over the allowed values of P, looking for a valid PLL configuration
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# that gives the desired "sys" frequency.
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fallback = None
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for P in mcu.range_p:
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# VCO_OUT must be between 192MHz and 432MHz
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if not sys * P in mcu.range_vco_out:
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continue
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NbyM = float(sys * P) / hse # float for Python 2
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# scan M
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M_min = mcu.range_n[0] // int(round(NbyM)) # starting value
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while mcu.range_vco_in[-1] * M_min < hse:
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M_min += 1
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# VCO_IN must be >=1MHz, but higher is better for stability so start high (low M)
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for M in range(M_min, hse + 1):
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# compute N
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N = NbyM * M
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# N must be an integer
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if not close_int(N):
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continue
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N = round(N)
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# N is restricted
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if N not in mcu.range_n:
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continue
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Q = float(sys * P) / 48 # float for Python 2
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# Q must be an integer in a set range
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if close_int(Q) and round(Q) in mcu.range_q:
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# found valid values
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return (M, N, P, Q)
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# Re-try Q to get at most 48MHz
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Q = (sys * P + 47) // 48
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if Q not in mcu.range_q:
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continue
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if fallback is None:
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# the values don't give 48MHz on PLL48 but are otherwise OK
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fallback = M, N, P, Q
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if relax_pll48:
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# might have found values which don't give 48MHz on PLL48
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return fallback
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else:
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# no valid values found which give 48MHz on PLL48
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return None
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def compute_derived(hse, pll):
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hse = float(hse) # float for Python 2
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M, N, P, Q = pll
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vco_in = hse / M
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vco_out = hse * N / M
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pllck = hse / M * N / P
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pll48ck = hse / M * N / Q
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return (vco_in, vco_out, pllck, pll48ck)
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def verify_pll(hse, pll):
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M, N, P, Q = pll
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vco_in, vco_out, pllck, pll48ck = compute_derived(hse, pll)
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# verify ints
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assert close_int(M)
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assert close_int(N)
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assert close_int(P)
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assert close_int(Q)
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# verify range
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assert M in mcu.range_m
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assert N in mcu.range_n
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assert P in mcu.range_p
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assert Q in mcu.range_q
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assert mcu.range_vco_in[0] <= vco_in <= mcu.range_vco_in[-1]
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assert mcu.range_vco_out[0] <= vco_out <= mcu.range_vco_out[-1]
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def compute_pll_table(source_clk, relax_pll48):
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valid_plls = []
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for sysclk in mcu.range_sysclk:
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pll = compute_pll2(source_clk, sysclk, relax_pll48)
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if pll is not None:
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verify_pll(source_clk, pll)
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valid_plls.append((sysclk, pll))
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return valid_plls
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def generate_c_table(hse, valid_plls):
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valid_plls.sort()
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if mcu.range_sysclk[-1] <= 0xff and mcu.range_m[-1] <= 0x3f and mcu.range_p[-1] // 2 - 1 <= 0x3:
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typedef = 'uint16_t'
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sys_mask = 0xff
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m_shift = 10
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m_mask = 0x3f
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p_shift = 8
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p_mask = 0x3
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else:
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typedef = 'uint32_t'
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sys_mask = 0xffff
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m_shift = 24
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m_mask = 0xff
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p_shift = 16
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p_mask = 0xff
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print("#define PLL_FREQ_TABLE_SYS(pll) ((pll) & %d)" % (sys_mask,))
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print("#define PLL_FREQ_TABLE_M(pll) (((pll) >> %d) & %d)" % (m_shift, m_mask))
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print("#define PLL_FREQ_TABLE_P(pll) (((((pll) >> %d) & %d) + 1) * 2)" % (p_shift, p_mask))
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print("typedef %s pll_freq_table_t;" % (typedef,))
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print("// (M, P/2-1, SYS) values for %u MHz source" % hse)
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print("static const pll_freq_table_t pll_freq_table[%u] = {" % (len(valid_plls),))
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for sys, (M, N, P, Q) in valid_plls:
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print(" (%u << %u) | (%u << %u) | %u," % (M, m_shift, P // 2 - 1, p_shift, sys), end='')
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if M >= 2:
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vco_in, vco_out, pllck, pll48ck = compute_derived(hse, (M, N, P, Q))
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print(" // M=%u N=%u P=%u Q=%u vco_in=%.2f vco_out=%.2f pll48=%.2f"
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% (M, N, P, Q, vco_in, vco_out, pll48ck), end=''
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)
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print()
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print("};")
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def print_table(hse, valid_plls):
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print("HSE =", hse, "MHz")
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print("sys : M N P Q : VCO_IN VCO_OUT PLLCK PLL48CK")
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out_format = "%3u : %2u %.1f %.2f %.2f : %5.2f %6.2f %6.2f %6.2f"
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for sys, pll in valid_plls:
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print(out_format % ((sys,) + pll + compute_derived(hse, pll)))
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print("found %u valid configurations" % len(valid_plls))
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def search_header_for_hsx_values(filename, vals):
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regex_inc = re.compile(r'#include "(boards/[A-Za-z0-9_./]+)"')
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regex_def = re.compile(r'#define +(HSE_VALUE|HSI_VALUE) +\((\(uint32_t\))?([0-9]+)\)')
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with open(filename) as f:
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for line in f:
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line = line.strip()
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m = regex_inc.match(line)
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if m:
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# Search included file
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search_header_for_hsx_values(m.group(1), vals)
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continue
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m = regex_def.match(line)
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if m:
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# Found HSE_VALUE or HSI_VALUE
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val = int(m.group(3)) // 1000000
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if m.group(1) == 'HSE_VALUE':
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vals[0] = val
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else:
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vals[1] = val
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return vals
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def main():
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global mcu
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global out_format
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# parse input args
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import sys
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argv = sys.argv[1:]
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c_table = False
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mcu_series = 'f4'
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hse = None
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hsi = None
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while True:
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if argv[0] == '-c':
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c_table = True
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argv.pop(0)
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elif argv[0] == '-m':
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argv.pop(0)
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mcu_series = argv.pop(0).lower()
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else:
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break
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if len(argv) != 1:
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print("usage: pllvalues.py [-c] [-m <mcu_series>] <hse in MHz>")
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sys.exit(1)
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if argv[0].startswith("file:"):
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# extract HSE_VALUE, and optionally HSI_VALUE, from header file
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hse, hsi = search_header_for_hsx_values(argv[0][5:], [None, None])
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if hse is None:
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raise ValueError("%s does not contain a definition of HSE_VALUE" % argv[0])
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if hsi is not None and hsi > 16:
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# Currently, a HSI value greater than 16MHz is not supported
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hsi = None
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else:
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# HSE given directly as an integer
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hse = int(argv[0])
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# Select MCU parameters
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if mcu_series == 'h7':
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mcu = mcu_h7
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else:
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mcu = mcu_default
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# Relax constraight on PLLQ being 48MHz on F7 and H7 MCUs, which have separate PLLs for 48MHz
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relax_pll48 = mcu_series in ('f7', 'h7')
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hse_valid_plls = compute_pll_table(hse, relax_pll48)
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if hsi is not None:
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hsi_valid_plls = compute_pll_table(hsi, relax_pll48)
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if c_table:
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print('#if MICROPY_HW_CLK_USE_HSI')
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if hsi is not None:
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hsi_valid_plls.append((hsi, (0, 0, 2, 0)))
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generate_c_table(hsi, hsi_valid_plls)
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print('#else')
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if hsi is not None:
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hse_valid_plls.append((hsi, (0, 0, 2, 0)))
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hse_valid_plls.append((hse, (1, 0, 2, 0)))
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generate_c_table(hse, hse_valid_plls)
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print('#endif')
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else:
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print_table(hse, hse_valid_plls)
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if __name__ == "__main__":
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main()
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