circuitpython/ports/mimxrt10xx/supervisor
Scott Shawcroft 5bb8a7a7c6
Improve iMX RT performance
* Enable dcache for OCRAM where the VM heap lives.
* Add CIRCUITPY_SWO_TRACE for pushing program counters out over the
  SWO pin via the ITM module in the CPU. Exempt some functions from
  instrumentation to reduce traffic and allow inlining.
* Place more functions in ITCM to handle errors using code in RAM-only
  and speed up CP.
* Use SET and CLEAR registers for digitalio. The SDK does read, mask
  and write.
* Switch to 2MiB reserved for CircuitPython code. Up from 1MiB.
* Run USB interrupts during flash erase and write.
* Allow storage writes from CP if the USB drive is disabled.
* Get perf bench tests running on CircuitPython and increase timeouts
  so it works when instrumentation is active.
2023-03-14 12:30:58 -07:00
..
cpu.S Add initial MIMXRT10XX port 2020-01-06 21:08:49 +01:00
flexspi_nor_flash_ops.c Improve iMX RT performance 2023-03-14 12:30:58 -07:00
internal_flash_root_pointers.h Add initial MIMXRT10XX port 2020-01-06 21:08:49 +01:00
internal_flash.c Improve iMX RT performance 2023-03-14 12:30:58 -07:00
internal_flash.h Improve iMX RT performance 2023-03-14 12:30:58 -07:00
port.c Improve iMX RT performance 2023-03-14 12:30:58 -07:00
usb.c Improve iMX RT performance 2023-03-14 12:30:58 -07:00