3eff81288c
Before this patch I2C transactions using a hardware I2C peripheral on F0/F7 MCUs would not correctly generate the I2C restart condition, and instead would generate a stop followed by a start. This is because the CR2 AUTOEND bit was being set before CR2 START when the peripheral already had the I2C bus from a previous transaction that did not generate a stop. As a consequence all combined transactions, eg read-then-write for an I2C memory transfer, generated a stop condition after the first transaction and didn't generate a stop at the very end (but still released the bus). Some I2C devices require a repeated start to function correctly. This patch fixes this by making sure the CR2 AUTOEND bit is set after the start condition and slave address have been fully transferred out.
491 lines
14 KiB
C
491 lines
14 KiB
C
/*
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* This file is part of the MicroPython project, http://micropython.org/
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2018 Damien P. George
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "py/mperrno.h"
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#include "py/mphal.h"
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#include "i2c.h"
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#if MICROPY_HW_ENABLE_HW_I2C
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#if defined(STM32F4)
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STATIC uint16_t i2c_timeout_ms[MICROPY_HW_MAX_I2C];
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int i2c_init(i2c_t *i2c, mp_hal_pin_obj_t scl, mp_hal_pin_obj_t sda, uint32_t freq, uint16_t timeout_ms) {
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uint32_t i2c_id = ((uint32_t)i2c - I2C1_BASE) / (I2C2_BASE - I2C1_BASE);
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// Init pins
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if (!mp_hal_pin_config_alt(scl, MP_HAL_PIN_MODE_ALT_OPEN_DRAIN, MP_HAL_PIN_PULL_UP, AF_FN_I2C, i2c_id + 1)) {
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return -MP_EPERM;
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}
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if (!mp_hal_pin_config_alt(sda, MP_HAL_PIN_MODE_ALT_OPEN_DRAIN, MP_HAL_PIN_PULL_UP, AF_FN_I2C, i2c_id + 1)) {
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return -MP_EPERM;
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}
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// Save timeout value
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i2c_timeout_ms[i2c_id] = timeout_ms;
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// Force reset I2C peripheral
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RCC->APB1RSTR |= RCC_APB1RSTR_I2C1RST << i2c_id;
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RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST << i2c_id);
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// Enable I2C peripheral clock
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RCC->APB1ENR |= RCC_APB1ENR_I2C1EN << i2c_id;
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volatile uint32_t tmp = RCC->APB1ENR; // delay after RCC clock enable
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(void)tmp;
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uint32_t PCLK1 = HAL_RCC_GetPCLK1Freq();
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// Initialise I2C peripheral
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i2c->CR1 = 0;
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i2c->CR2 = PCLK1 / 1000000;
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i2c->OAR1 = 0;
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i2c->OAR2 = 0;
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freq = MIN(freq, 400000);
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// SM: MAX(4, PCLK1 / (F * 2))
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// FM, 16:9 duty: 0xc000 | MAX(1, (PCLK1 / (F * (16 + 9))))
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if (freq <= 100000) {
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i2c->CCR = MAX(4, PCLK1 / (freq * 2));
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} else {
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i2c->CCR = 0xc000 | MAX(1, PCLK1 / (freq * 25));
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}
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// SM: 1000ns / (1/PCLK1) + 1 = PCLK1 * 1e-6 + 1
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// FM: 300ns / (1/PCLK1) + 1 = 300e-3 * PCLK1 * 1e-6 + 1
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if (freq <= 100000) {
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i2c->TRISE = PCLK1 / 1000000 + 1; // 1000ns rise time in SM
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} else {
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i2c->TRISE = PCLK1 / 1000000 * 3 / 10 + 1; // 300ns rise time in FM
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}
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#if defined(I2C_FLTR_ANOFF)
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i2c->FLTR = 0; // analog filter on, digital filter off
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#endif
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return 0;
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}
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STATIC int i2c_wait_sr1_set(i2c_t *i2c, uint32_t mask) {
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uint32_t i2c_id = ((uint32_t)i2c - I2C1_BASE) / (I2C2_BASE - I2C1_BASE);
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uint32_t t0 = HAL_GetTick();
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while (!(i2c->SR1 & mask)) {
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if (HAL_GetTick() - t0 >= i2c_timeout_ms[i2c_id]) {
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i2c->CR1 &= ~I2C_CR1_PE;
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return -MP_ETIMEDOUT;
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}
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}
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return 0;
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}
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STATIC int i2c_wait_stop(i2c_t *i2c) {
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uint32_t i2c_id = ((uint32_t)i2c - I2C1_BASE) / (I2C2_BASE - I2C1_BASE);
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uint32_t t0 = HAL_GetTick();
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while (i2c->CR1 & I2C_CR1_STOP) {
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if (HAL_GetTick() - t0 >= i2c_timeout_ms[i2c_id]) {
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i2c->CR1 &= ~I2C_CR1_PE;
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return -MP_ETIMEDOUT;
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}
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}
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i2c->CR1 &= ~I2C_CR1_PE;
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return 0;
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}
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// For write: len = 0, 1 or N
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// For read: len = 1, 2 or N; stop = true
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int i2c_start_addr(i2c_t *i2c, int rd_wrn, uint16_t addr, size_t next_len, bool stop) {
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if (!(i2c->CR1 & I2C_CR1_PE) && (i2c->SR2 & I2C_SR2_MSL)) {
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// The F4 I2C peripheral can sometimes get into a bad state where it's disabled
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// (PE low) but still an active master (MSL high). It seems the best way to get
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// out of this is a full reset.
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uint32_t i2c_id = ((uint32_t)i2c - I2C1_BASE) / (I2C2_BASE - I2C1_BASE);
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RCC->APB1RSTR |= RCC_APB1RSTR_I2C1RST << i2c_id;
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RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST << i2c_id);
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}
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// It looks like it's possible to terminate the reading by sending a
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// START condition instead of STOP condition but we don't support that.
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if (rd_wrn) {
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if (!stop) {
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return -MP_EINVAL;
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}
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}
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// Repurpose OAR1 to hold stop flag
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i2c->OAR1 = stop;
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// Enable peripheral and send START condition
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i2c->CR1 |= I2C_CR1_PE;
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i2c->CR1 |= I2C_CR1_START;
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// Wait for START to be sent
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int ret;
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if ((ret = i2c_wait_sr1_set(i2c, I2C_SR1_SB))) {
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return ret;
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}
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// Send the 7-bit address with read/write bit
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i2c->DR = addr << 1 | rd_wrn;
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// Wait for address to be sent
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if ((ret = i2c_wait_sr1_set(i2c, I2C_SR1_AF | I2C_SR1_ADDR))) {
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return ret;
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}
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// Check if the slave responded or not
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if (i2c->SR1 & I2C_SR1_AF) {
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// Got a NACK
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i2c->CR1 |= I2C_CR1_STOP;
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i2c_wait_stop(i2c); // Don't leak errors from this call
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return -MP_ENODEV;
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}
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if (rd_wrn) {
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// For reading, set up ACK/NACK control based on number of bytes to read (at least 1 byte)
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if (next_len <= 1) {
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// NACK next received byte
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i2c->CR1 &= ~I2C_CR1_ACK;
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} else if (next_len <= 2) {
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// NACK second received byte
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i2c->CR1 |= I2C_CR1_POS;
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i2c->CR1 &= ~I2C_CR1_ACK;
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} else {
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// ACK next received byte
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i2c->CR1 |= I2C_CR1_ACK;
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}
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}
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// Read SR2 to clear SR1_ADDR
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uint32_t sr2 = i2c->SR2;
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(void)sr2;
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return 0;
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}
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// next_len = 0 or N (>=2)
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int i2c_read(i2c_t *i2c, uint8_t *dest, size_t len, size_t next_len) {
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if (len == 0) {
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return -MP_EINVAL;
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}
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if (next_len == 1) {
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return -MP_EINVAL;
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}
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size_t remain = len + next_len;
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if (remain == 1) {
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// Special case
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i2c->CR1 |= I2C_CR1_STOP;
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int ret;
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if ((ret = i2c_wait_sr1_set(i2c, I2C_SR1_RXNE))) {
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return ret;
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}
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*dest = i2c->DR;
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} else {
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for (; len; --len) {
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remain = len + next_len;
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int ret;
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if ((ret = i2c_wait_sr1_set(i2c, I2C_SR1_BTF))) {
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return ret;
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}
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if (remain == 2) {
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// In this case next_len == 0 (it's not allowed to be 1)
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i2c->CR1 |= I2C_CR1_STOP;
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*dest++ = i2c->DR;
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*dest = i2c->DR;
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break;
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} else if (remain == 3) {
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// NACK next received byte
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i2c->CR1 &= ~I2C_CR1_ACK;
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}
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*dest++ = i2c->DR;
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}
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}
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if (!next_len) {
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// We sent a stop above, just wait for it to be finished
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return i2c_wait_stop(i2c);
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}
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return 0;
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}
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// next_len = 0 or N
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int i2c_write(i2c_t *i2c, const uint8_t *src, size_t len, size_t next_len) {
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int ret;
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if ((ret = i2c_wait_sr1_set(i2c, I2C_SR1_AF | I2C_SR1_TXE))) {
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return ret;
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}
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// Write out the data
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int num_acks = 0;
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while (len--) {
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i2c->DR = *src++;
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if ((ret = i2c_wait_sr1_set(i2c, I2C_SR1_AF | I2C_SR1_BTF))) {
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return ret;
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}
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if (i2c->SR1 & I2C_SR1_AF) {
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// Slave did not respond to byte so stop sending
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break;
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}
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++num_acks;
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}
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if (!next_len) {
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if (i2c->OAR1) {
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// Send a STOP and wait for it to finish
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i2c->CR1 |= I2C_CR1_STOP;
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if ((ret = i2c_wait_stop(i2c))) {
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return ret;
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}
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}
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}
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return num_acks;
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}
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#elif defined(STM32F0) || defined(STM32F7)
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STATIC uint16_t i2c_timeout_ms[MICROPY_HW_MAX_I2C];
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int i2c_init(i2c_t *i2c, mp_hal_pin_obj_t scl, mp_hal_pin_obj_t sda, uint32_t freq, uint16_t timeout_ms) {
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uint32_t i2c_id = ((uint32_t)i2c - I2C1_BASE) / (I2C2_BASE - I2C1_BASE);
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// Init pins
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if (!mp_hal_pin_config_alt(scl, MP_HAL_PIN_MODE_ALT_OPEN_DRAIN, MP_HAL_PIN_PULL_UP, AF_FN_I2C, i2c_id + 1)) {
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return -MP_EPERM;
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}
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if (!mp_hal_pin_config_alt(sda, MP_HAL_PIN_MODE_ALT_OPEN_DRAIN, MP_HAL_PIN_PULL_UP, AF_FN_I2C, i2c_id + 1)) {
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return -MP_EPERM;
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}
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// Save timeout value
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i2c_timeout_ms[i2c_id] = timeout_ms;
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// Enable I2C peripheral clock
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RCC->APB1ENR |= RCC_APB1ENR_I2C1EN << i2c_id;
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volatile uint32_t tmp = RCC->APB1ENR; // delay after RCC clock enable
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(void)tmp;
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// Initialise I2C peripheral
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i2c->CR1 = 0;
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i2c->CR2 = 0;
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i2c->OAR1 = 0;
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i2c->OAR2 = 0;
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// These timing values are for f_I2CCLK=54MHz and are only approximate
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if (freq >= 1000000) {
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i2c->TIMINGR = 0x50100103;
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} else if (freq >= 400000) {
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i2c->TIMINGR = 0x70330309;
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} else if (freq >= 100000) {
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i2c->TIMINGR = 0xb0420f13;
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} else {
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return -MP_EINVAL;
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}
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i2c->TIMEOUTR = 0;
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return 0;
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}
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STATIC int i2c_wait_cr2_clear(i2c_t *i2c, uint32_t mask) {
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uint32_t i2c_id = ((uint32_t)i2c - I2C1_BASE) / (I2C2_BASE - I2C1_BASE);
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uint32_t t0 = HAL_GetTick();
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while (i2c->CR2 & mask) {
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if (HAL_GetTick() - t0 >= i2c_timeout_ms[i2c_id]) {
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i2c->CR1 &= ~I2C_CR1_PE;
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return -MP_ETIMEDOUT;
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}
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}
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return 0;
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}
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STATIC int i2c_wait_isr_set(i2c_t *i2c, uint32_t mask) {
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uint32_t i2c_id = ((uint32_t)i2c - I2C1_BASE) / (I2C2_BASE - I2C1_BASE);
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uint32_t t0 = HAL_GetTick();
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while (!(i2c->ISR & mask)) {
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if (HAL_GetTick() - t0 >= i2c_timeout_ms[i2c_id]) {
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i2c->CR1 &= ~I2C_CR1_PE;
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return -MP_ETIMEDOUT;
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}
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}
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return 0;
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}
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// len = 0, 1 or N
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int i2c_start_addr(i2c_t *i2c, int rd_wrn, uint16_t addr, size_t len, bool stop) {
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// Enable the peripheral and send the START condition with slave address
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i2c->CR1 |= I2C_CR1_PE;
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i2c->CR2 = (len > 1) << I2C_CR2_RELOAD_Pos
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| (len > 0) << I2C_CR2_NBYTES_Pos
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| rd_wrn << I2C_CR2_RD_WRN_Pos
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| (addr & 0x7f) << 1;
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i2c->CR2 |= I2C_CR2_START;
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// Wait for address to be sent
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int ret;
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if ((ret = i2c_wait_cr2_clear(i2c, I2C_CR2_START))) {
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return ret;
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}
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// Check if the slave responded or not
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if (i2c->ISR & I2C_ISR_NACKF) {
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// If we get a NACK then I2C periph unconditionally sends a STOP
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i2c_wait_isr_set(i2c, I2C_ISR_STOPF); // Don't leak errors from this call
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i2c->CR1 &= ~I2C_CR1_PE;
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return -MP_ENODEV;
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}
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// Configure automatic STOP if needed
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if (stop) {
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i2c->CR2 |= I2C_CR2_AUTOEND;
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}
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// Repurpose OAR1 to indicate that we loaded CR2
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i2c->OAR1 = 1;
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return 0;
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}
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STATIC int i2c_check_stop(i2c_t *i2c) {
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if (i2c->CR2 & I2C_CR2_AUTOEND) {
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// Wait for the STOP condition and then disable the peripheral
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int ret;
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if ((ret = i2c_wait_isr_set(i2c, I2C_ISR_STOPF))) {
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return ret;
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}
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i2c->CR1 &= ~I2C_CR1_PE;
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}
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return 0;
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}
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// next_len = 0 or N
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int i2c_read(i2c_t *i2c, uint8_t *dest, size_t len, size_t next_len) {
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if (i2c->OAR1) {
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i2c->OAR1 = 0;
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} else {
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goto load_cr2;
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}
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// Read in the data
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while (len--) {
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int ret;
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if ((ret = i2c_wait_isr_set(i2c, I2C_ISR_RXNE))) {
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return ret;
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}
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*dest++ = i2c->RXDR;
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load_cr2:
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if (len) {
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i2c->CR2 = (i2c->CR2 & I2C_CR2_AUTOEND)
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| (len + next_len > 1) << I2C_CR2_RELOAD_Pos
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| 1 << I2C_CR2_NBYTES_Pos;
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}
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}
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if (!next_len) {
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int ret;
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if ((ret = i2c_check_stop(i2c))) {
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return ret;
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}
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}
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return 0;
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}
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// next_len = 0 or N
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int i2c_write(i2c_t *i2c, const uint8_t *src, size_t len, size_t next_len) {
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int num_acks = 0;
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if (i2c->OAR1) {
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i2c->OAR1 = 0;
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} else {
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goto load_cr2;
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}
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// Write out the data
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while (len--) {
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int ret;
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if ((ret = i2c_wait_isr_set(i2c, I2C_ISR_TXE))) {
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return ret;
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}
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i2c->TXDR = *src++;
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if ((ret = i2c_wait_isr_set(i2c, I2C_ISR_TCR | I2C_ISR_TC | I2C_ISR_STOPF))) {
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return ret;
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}
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uint32_t isr = i2c->ISR;
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if (isr & I2C_ISR_NACKF) {
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// Slave did not respond to byte so stop sending
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if (!(isr & I2C_ISR_TXE)) {
|
|
// The TXDR is still full so the byte previous to that wasn't actually ACK'd
|
|
--num_acks;
|
|
}
|
|
break;
|
|
}
|
|
++num_acks;
|
|
load_cr2:
|
|
if (len) {
|
|
i2c->CR2 = (i2c->CR2 & I2C_CR2_AUTOEND)
|
|
| (len + next_len > 1) << I2C_CR2_RELOAD_Pos
|
|
| 1 << I2C_CR2_NBYTES_Pos;
|
|
}
|
|
}
|
|
|
|
if (!next_len) {
|
|
int ret;
|
|
if ((ret = i2c_check_stop(i2c))) {
|
|
return ret;
|
|
}
|
|
}
|
|
|
|
return num_acks;
|
|
}
|
|
|
|
#endif
|
|
|
|
#if defined(STM32F0) || defined(STM32F4) || defined(STM32F7)
|
|
|
|
int i2c_readfrom(i2c_t *i2c, uint16_t addr, uint8_t *dest, size_t len, bool stop) {
|
|
int ret;
|
|
if ((ret = i2c_start_addr(i2c, 1, addr, len, stop))) {
|
|
return ret;
|
|
}
|
|
return i2c_read(i2c, dest, len, 0);
|
|
}
|
|
|
|
int i2c_writeto(i2c_t *i2c, uint16_t addr, const uint8_t *src, size_t len, bool stop) {
|
|
int ret;
|
|
if ((ret = i2c_start_addr(i2c, 0, addr, len, stop))) {
|
|
return ret;
|
|
}
|
|
return i2c_write(i2c, src, len, 0);
|
|
}
|
|
|
|
#endif
|
|
|
|
#endif // MICROPY_HW_ENABLE_HW_I2C
|