0621eca05e
Only those files which are needed by the stmhal port are added. Also includes a dummy file (stm32f2xx_hal_pcd_ex.c) to keep the build system the same for f4 and f2 MCU series.
739 lines
33 KiB
C
739 lines
33 KiB
C
/**
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******************************************************************************
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* @file stm32f2xx_hal_adc.h
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* @author MCD Application Team
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* @version V1.0.1
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* @date 25-March-2014
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* @brief Header file of ADC HAL extension module.
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of STMicroelectronics nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __STM32F2xx_ADC_H
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#define __STM32F2xx_ADC_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include "stm32f2xx_hal_def.h"
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/** @addtogroup STM32F2xx_HAL_Driver
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* @{
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*/
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/** @addtogroup ADC
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* @{
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*/
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/* Exported types ------------------------------------------------------------*/
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/**
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* @brief HAL State structures definition
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*/
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typedef enum
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{
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HAL_ADC_STATE_RESET = 0x00, /*!< ADC not yet initialized or disabled */
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HAL_ADC_STATE_READY = 0x01, /*!< ADC peripheral ready for use */
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HAL_ADC_STATE_BUSY = 0x02, /*!< An internal process is ongoing */
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HAL_ADC_STATE_BUSY_REG = 0x12, /*!< Regular conversion is ongoing */
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HAL_ADC_STATE_BUSY_INJ = 0x22, /*!< Injected conversion is ongoing */
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HAL_ADC_STATE_BUSY_INJ_REG = 0x32, /*!< Injected and regular conversion are ongoing */
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HAL_ADC_STATE_TIMEOUT = 0x03, /*!< Timeout state */
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HAL_ADC_STATE_ERROR = 0x04, /*!< ADC state error */
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HAL_ADC_STATE_EOC = 0x05, /*!< Conversion is completed */
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HAL_ADC_STATE_EOC_REG = 0x15, /*!< Regular conversion is completed */
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HAL_ADC_STATE_EOC_INJ = 0x25, /*!< Injected conversion is completed */
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HAL_ADC_STATE_EOC_INJ_REG = 0x35, /*!< Injected and regular conversion are completed */
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HAL_ADC_STATE_AWD = 0x06 /*!< ADC state analog watchdog */
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}HAL_ADC_StateTypeDef;
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/**
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* @brief ADC Init structure definition
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*/
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typedef struct
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{
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uint32_t ClockPrescaler; /*!< Select the frequency of the clock to the ADC. The clock is common for
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all the ADCs.
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This parameter can be a value of @ref ADC_ClockPrescaler */
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uint32_t Resolution; /*!< Configures the ADC resolution dual mode.
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This parameter can be a value of @ref ADC_Resolution */
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uint32_t DataAlign; /*!< Specifies whether the ADC data alignment is left or right.
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This parameter can be a value of @ref ADC_data_align */
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uint32_t ScanConvMode; /*!< Specifies whether the conversion is performed in Scan (multi channels) or
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Single (one channel) mode.
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This parameter can be set to ENABLE or DISABLE */
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uint32_t EOCSelection; /*!< Specifies whether the EOC flag is set
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at the end of single channel conversion or at the end of all conversions.
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This parameter can be a value of @ref ADC_EOCSelection */
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uint32_t ContinuousConvMode; /*!< Specifies whether the conversion is performed in Continuous or Single mode.
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This parameter can be set to ENABLE or DISABLE. */
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uint32_t DMAContinuousRequests; /*!< Specifies whether the DMA requests is performed in Continuous or in Single mode.
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This parameter can be set to ENABLE or DISABLE. */
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uint32_t NbrOfConversion; /*!< Specifies the number of ADC conversions that will be done using the sequencer for
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regular channel group.
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This parameter must be a number between Min_Data = 1 and Max_Data = 16. */
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uint32_t DiscontinuousConvMode; /*!< Specifies whether the conversion is performed in Discontinuous or not
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for regular channels.
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This parameter can be set to ENABLE or DISABLE. */
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uint32_t NbrOfDiscConversion; /*!< Specifies the number of ADC discontinuous conversions that will be done
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using the sequencer for regular channel group.
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This parameter must be a number between Min_Data = 1 and Max_Data = 8. */
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uint32_t ExternalTrigConvEdge; /*!< Select the external trigger edge and enable the trigger of a regular group.
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This parameter can be a value of @ref ADC_External_trigger_edge_Regular */
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uint32_t ExternalTrigConv; /*!< Select the external event used to trigger the start of conversion of a regular group.
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This parameter can be a value of @ref ADC_External_trigger_Source_Regular */
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}ADC_InitTypeDef;
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/**
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* @brief ADC handle Structure definition
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*/
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typedef struct
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{
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ADC_TypeDef *Instance; /*!< Register base address */
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ADC_InitTypeDef Init; /*!< ADC required parameters */
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__IO uint32_t NbrOfCurrentConversionRank; /*!< ADC number of current conversion rank */
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DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */
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HAL_LockTypeDef Lock; /*!< ADC locking object */
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__IO HAL_ADC_StateTypeDef State; /*!< ADC communication state */
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__IO uint32_t ErrorCode; /*!< ADC Error code */
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}ADC_HandleTypeDef;
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/**
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* @brief ADC Configuration regular Channel structure definition
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*/
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typedef struct
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{
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uint32_t Channel; /*!< The ADC channel to configure
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This parameter can be a value of @ref ADC_channels */
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uint32_t Rank; /*!< The rank in the regular group sequencer
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This parameter must be a number between Min_Data = 1 and Max_Data = 16 */
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uint32_t SamplingTime; /*!< The sample time value to be set for the selected channel.
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This parameter can be a value of @ref ADC_sampling_times */
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uint32_t Offset; /*!< Reserved for future use, can be set to 0 */
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}ADC_ChannelConfTypeDef;
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/**
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* @brief ADC Configuration multi-mode structure definition
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*/
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typedef struct
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{
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uint32_t WatchdogMode; /*!< Configures the ADC analog watchdog mode.
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This parameter can be a value of @ref ADC_analog_watchdog_selection. */
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uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value.
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This parameter must be a 12-bit value. */
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uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value.
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This parameter must be a 12-bit value. */
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uint32_t Channel; /*!< Configures ADC channel for the analog watchdog.
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This parameter has an effect only if watchdog mode is configured on single channel
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This parameter can be a value of @ref ADC_channels. */
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uint32_t ITMode; /*!< Specifies whether the analog watchdog is configured
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is interrupt mode or in polling mode.
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This parameter can be set to ENABLE or DISABLE */
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uint32_t WatchdogNumber; /*!< Reserved for future use, can be set to 0 */
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}ADC_AnalogWDGConfTypeDef;
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/* Exported constants --------------------------------------------------------*/
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/** @defgroup ADC_Exported_Constants
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* @{
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*/
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/** @defgroup ADC_Error_Code
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* @{
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*/
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#define HAL_ADC_ERROR_NONE ((uint32_t)0x00) /*!< No error */
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#define HAL_ADC_ERROR_OVR ((uint32_t)0x01) /*!< OVR error */
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#define HAL_ADC_ERROR_DMA ((uint32_t)0x02) /*!< DMA transfer error */
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/**
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* @}
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*/
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/** @defgroup ADC_ClockPrescaler
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* @{
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*/
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#define ADC_CLOCKPRESCALER_PCLK_DIV2 ((uint32_t)0x00000000)
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#define ADC_CLOCKPRESCALER_PCLK_DIV4 ((uint32_t)ADC_CCR_ADCPRE_0)
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#define ADC_CLOCKPRESCALER_PCLK_DIV6 ((uint32_t)ADC_CCR_ADCPRE_1)
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#define ADC_CLOCKPRESCALER_PCLK_DIV8 ((uint32_t)ADC_CCR_ADCPRE)
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#define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCKPRESCALER_PCLK_DIV2) || \
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((ADC_CLOCK) == ADC_CLOCKPRESCALER_PCLK_DIV4) || \
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((ADC_CLOCK) == ADC_CLOCKPRESCALER_PCLK_DIV6) || \
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((ADC_CLOCK) == ADC_CLOCKPRESCALER_PCLK_DIV8))
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/**
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* @}
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*/
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/** @defgroup ADC_delay_between_2_sampling_phases
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* @{
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*/
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#define ADC_TWOSAMPLINGDELAY_5CYCLES ((uint32_t)0x00000000)
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#define ADC_TWOSAMPLINGDELAY_6CYCLES ((uint32_t)ADC_CCR_DELAY_0)
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#define ADC_TWOSAMPLINGDELAY_7CYCLES ((uint32_t)ADC_CCR_DELAY_1)
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#define ADC_TWOSAMPLINGDELAY_8CYCLES ((uint32_t)(ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
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#define ADC_TWOSAMPLINGDELAY_9CYCLES ((uint32_t)ADC_CCR_DELAY_2)
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#define ADC_TWOSAMPLINGDELAY_10CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0))
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#define ADC_TWOSAMPLINGDELAY_11CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1))
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#define ADC_TWOSAMPLINGDELAY_12CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
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#define ADC_TWOSAMPLINGDELAY_13CYCLES ((uint32_t)ADC_CCR_DELAY_3)
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#define ADC_TWOSAMPLINGDELAY_14CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0))
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#define ADC_TWOSAMPLINGDELAY_15CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1))
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#define ADC_TWOSAMPLINGDELAY_16CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
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#define ADC_TWOSAMPLINGDELAY_17CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2))
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#define ADC_TWOSAMPLINGDELAY_18CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0))
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#define ADC_TWOSAMPLINGDELAY_19CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1))
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#define ADC_TWOSAMPLINGDELAY_20CYCLES ((uint32_t)ADC_CCR_DELAY)
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#define IS_ADC_SAMPLING_DELAY(DELAY) (((DELAY) == ADC_TWOSAMPLINGDELAY_5CYCLES) || \
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((DELAY) == ADC_TWOSAMPLINGDELAY_6CYCLES) || \
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((DELAY) == ADC_TWOSAMPLINGDELAY_7CYCLES) || \
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((DELAY) == ADC_TWOSAMPLINGDELAY_8CYCLES) || \
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((DELAY) == ADC_TWOSAMPLINGDELAY_9CYCLES) || \
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((DELAY) == ADC_TWOSAMPLINGDELAY_10CYCLES) || \
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((DELAY) == ADC_TWOSAMPLINGDELAY_11CYCLES) || \
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((DELAY) == ADC_TWOSAMPLINGDELAY_12CYCLES) || \
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((DELAY) == ADC_TWOSAMPLINGDELAY_13CYCLES) || \
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((DELAY) == ADC_TWOSAMPLINGDELAY_14CYCLES) || \
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((DELAY) == ADC_TWOSAMPLINGDELAY_15CYCLES) || \
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((DELAY) == ADC_TWOSAMPLINGDELAY_16CYCLES) || \
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((DELAY) == ADC_TWOSAMPLINGDELAY_17CYCLES) || \
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((DELAY) == ADC_TWOSAMPLINGDELAY_18CYCLES) || \
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((DELAY) == ADC_TWOSAMPLINGDELAY_19CYCLES) || \
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((DELAY) == ADC_TWOSAMPLINGDELAY_20CYCLES))
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/**
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* @}
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*/
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/** @defgroup ADC_Resolution
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* @{
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*/
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#define ADC_RESOLUTION12b ((uint32_t)0x00000000)
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#define ADC_RESOLUTION10b ((uint32_t)ADC_CR1_RES_0)
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#define ADC_RESOLUTION8b ((uint32_t)ADC_CR1_RES_1)
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#define ADC_RESOLUTION6b ((uint32_t)ADC_CR1_RES)
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#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION12b) || \
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((RESOLUTION) == ADC_RESOLUTION10b) || \
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((RESOLUTION) == ADC_RESOLUTION8b) || \
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((RESOLUTION) == ADC_RESOLUTION6b))
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/**
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* @}
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*/
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/** @defgroup ADC_External_trigger_edge_Regular
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* @{
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*/
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#define ADC_EXTERNALTRIGCONVEDGE_NONE ((uint32_t)0x00000000)
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#define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTEN_0)
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#define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CR2_EXTEN_1)
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#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CR2_EXTEN)
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#define IS_ADC_EXT_TRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \
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((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \
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((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \
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((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING))
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/**
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* @}
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*/
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/** @defgroup ADC_External_trigger_Source_Regular
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* @{
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*/
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#define ADC_EXTERNALTRIGCONV_T1_CC1 ((uint32_t)0x00000000)
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#define ADC_EXTERNALTRIGCONV_T1_CC2 ((uint32_t)ADC_CR2_EXTSEL_0)
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#define ADC_EXTERNALTRIGCONV_T1_CC3 ((uint32_t)ADC_CR2_EXTSEL_1)
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#define ADC_EXTERNALTRIGCONV_T2_CC2 ((uint32_t)(ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
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#define ADC_EXTERNALTRIGCONV_T2_CC3 ((uint32_t)ADC_CR2_EXTSEL_2)
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#define ADC_EXTERNALTRIGCONV_T2_CC4 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0))
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#define ADC_EXTERNALTRIGCONV_T2_TRGO ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1))
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#define ADC_EXTERNALTRIGCONV_T3_CC1 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
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#define ADC_EXTERNALTRIGCONV_T3_TRGO ((uint32_t)ADC_CR2_EXTSEL_3)
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#define ADC_EXTERNALTRIGCONV_T4_CC4 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_0))
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#define ADC_EXTERNALTRIGCONV_T5_CC1 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1))
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#define ADC_EXTERNALTRIGCONV_T5_CC2 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
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#define ADC_EXTERNALTRIGCONV_T5_CC3 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2))
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#define ADC_EXTERNALTRIGCONV_T8_CC1 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0))
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#define ADC_EXTERNALTRIGCONV_T8_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1))
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#define ADC_EXTERNALTRIGCONV_Ext_IT11 ((uint32_t)ADC_CR2_EXTSEL)
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#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \
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((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \
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((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3) || \
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((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \
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((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC3) || \
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((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC4) || \
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((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \
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((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC1) || \
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((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \
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((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \
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((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC1) || \
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((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC2) || \
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((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC3) || \
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((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_CC1) || \
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((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO) || \
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((REGTRIG) == ADC_EXTERNALTRIGCONV_Ext_IT11))
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/**
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* @}
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*/
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/** @defgroup ADC_data_align
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* @{
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*/
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#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000)
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#define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CR2_ALIGN)
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#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \
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((ALIGN) == ADC_DATAALIGN_LEFT))
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/**
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* @}
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*/
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/** @defgroup ADC_channels
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* @{
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*/
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#define ADC_CHANNEL_0 ((uint32_t)0x00000000)
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#define ADC_CHANNEL_1 ((uint32_t)ADC_CR1_AWDCH_0)
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#define ADC_CHANNEL_2 ((uint32_t)ADC_CR1_AWDCH_1)
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#define ADC_CHANNEL_3 ((uint32_t)(ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
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#define ADC_CHANNEL_4 ((uint32_t)ADC_CR1_AWDCH_2)
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#define ADC_CHANNEL_5 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0))
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#define ADC_CHANNEL_6 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1))
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#define ADC_CHANNEL_7 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
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#define ADC_CHANNEL_8 ((uint32_t)ADC_CR1_AWDCH_3)
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#define ADC_CHANNEL_9 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_0))
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#define ADC_CHANNEL_10 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1))
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#define ADC_CHANNEL_11 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
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#define ADC_CHANNEL_12 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2))
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#define ADC_CHANNEL_13 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0))
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#define ADC_CHANNEL_14 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1))
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#define ADC_CHANNEL_15 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
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#define ADC_CHANNEL_16 ((uint32_t)ADC_CR1_AWDCH_4)
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#define ADC_CHANNEL_17 ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_0))
|
|
#define ADC_CHANNEL_18 ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_1))
|
|
|
|
#define ADC_CHANNEL_TEMPSENSOR ((uint32_t)ADC_CHANNEL_16)
|
|
#define ADC_CHANNEL_VREFINT ((uint32_t)ADC_CHANNEL_17)
|
|
#define ADC_CHANNEL_VBAT ((uint32_t)ADC_CHANNEL_18)
|
|
|
|
#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) || \
|
|
((CHANNEL) == ADC_CHANNEL_1) || \
|
|
((CHANNEL) == ADC_CHANNEL_2) || \
|
|
((CHANNEL) == ADC_CHANNEL_3) || \
|
|
((CHANNEL) == ADC_CHANNEL_4) || \
|
|
((CHANNEL) == ADC_CHANNEL_5) || \
|
|
((CHANNEL) == ADC_CHANNEL_6) || \
|
|
((CHANNEL) == ADC_CHANNEL_7) || \
|
|
((CHANNEL) == ADC_CHANNEL_8) || \
|
|
((CHANNEL) == ADC_CHANNEL_9) || \
|
|
((CHANNEL) == ADC_CHANNEL_10) || \
|
|
((CHANNEL) == ADC_CHANNEL_11) || \
|
|
((CHANNEL) == ADC_CHANNEL_12) || \
|
|
((CHANNEL) == ADC_CHANNEL_13) || \
|
|
((CHANNEL) == ADC_CHANNEL_14) || \
|
|
((CHANNEL) == ADC_CHANNEL_15) || \
|
|
((CHANNEL) == ADC_CHANNEL_16) || \
|
|
((CHANNEL) == ADC_CHANNEL_17) || \
|
|
((CHANNEL) == ADC_CHANNEL_18))
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup ADC_sampling_times
|
|
* @{
|
|
*/
|
|
#define ADC_SAMPLETIME_3CYCLES ((uint32_t)0x00000000)
|
|
#define ADC_SAMPLETIME_15CYCLES ((uint32_t)ADC_SMPR1_SMP10_0)
|
|
#define ADC_SAMPLETIME_28CYCLES ((uint32_t)ADC_SMPR1_SMP10_1)
|
|
#define ADC_SAMPLETIME_56CYCLES ((uint32_t)(ADC_SMPR1_SMP10_1 | ADC_SMPR1_SMP10_0))
|
|
#define ADC_SAMPLETIME_84CYCLES ((uint32_t)ADC_SMPR1_SMP10_2)
|
|
#define ADC_SAMPLETIME_112CYCLES ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_0))
|
|
#define ADC_SAMPLETIME_144CYCLES ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_1))
|
|
#define ADC_SAMPLETIME_480CYCLES ((uint32_t)ADC_SMPR1_SMP10)
|
|
|
|
#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_3CYCLES) || \
|
|
((TIME) == ADC_SAMPLETIME_15CYCLES) || \
|
|
((TIME) == ADC_SAMPLETIME_28CYCLES) || \
|
|
((TIME) == ADC_SAMPLETIME_56CYCLES) || \
|
|
((TIME) == ADC_SAMPLETIME_84CYCLES) || \
|
|
((TIME) == ADC_SAMPLETIME_112CYCLES) || \
|
|
((TIME) == ADC_SAMPLETIME_144CYCLES) || \
|
|
((TIME) == ADC_SAMPLETIME_480CYCLES))
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup ADC_EOCSelection
|
|
* @{
|
|
*/
|
|
#define EOC_SEQ_CONV ((uint32_t)0x00000000)
|
|
#define EOC_SINGLE_CONV ((uint32_t)0x00000001)
|
|
#define EOC_SINGLE_SEQ_CONV ((uint32_t)0x00000002) /*!< reserved for future use */
|
|
|
|
#define IS_ADC_EOCSelection(EOCSelection) (((EOCSelection) == EOC_SINGLE_CONV) || \
|
|
((EOCSelection) == EOC_SEQ_CONV) || \
|
|
((EOCSelection) == EOC_SINGLE_SEQ_CONV))
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup ADC_Event_type
|
|
* @{
|
|
*/
|
|
#define AWD_EVENT ((uint32_t)ADC_FLAG_AWD)
|
|
#define OVR_EVENT ((uint32_t)ADC_FLAG_OVR)
|
|
|
|
#define IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == AWD_EVENT) || \
|
|
((EVENT) == OVR_EVENT))
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup ADC_analog_watchdog_selection
|
|
* @{
|
|
*/
|
|
#define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN))
|
|
#define ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN))
|
|
#define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
|
|
#define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t)ADC_CR1_AWDEN)
|
|
#define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t)ADC_CR1_JAWDEN)
|
|
#define ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
|
|
#define ADC_ANALOGWATCHDOG_NONE ((uint32_t)0x00000000)
|
|
|
|
#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \
|
|
((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \
|
|
((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \
|
|
((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG) || \
|
|
((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \
|
|
((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) || \
|
|
((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE))
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup ADC_interrupts_definition
|
|
* @{
|
|
*/
|
|
#define ADC_IT_EOC ((uint32_t)ADC_CR1_EOCIE)
|
|
#define ADC_IT_AWD ((uint32_t)ADC_CR1_AWDIE)
|
|
#define ADC_IT_JEOC ((uint32_t)ADC_CR1_JEOCIE)
|
|
#define ADC_IT_OVR ((uint32_t)ADC_CR1_OVRIE)
|
|
|
|
#define IS_ADC_IT(IT) (((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_AWD) || \
|
|
((IT) == ADC_IT_JEOC)|| ((IT) == ADC_IT_OVR))
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup ADC_flags_definition
|
|
* @{
|
|
*/
|
|
#define ADC_FLAG_AWD ((uint32_t)ADC_SR_AWD)
|
|
#define ADC_FLAG_EOC ((uint32_t)ADC_SR_EOC)
|
|
#define ADC_FLAG_JEOC ((uint32_t)ADC_SR_JEOC)
|
|
#define ADC_FLAG_JSTRT ((uint32_t)ADC_SR_JSTRT)
|
|
#define ADC_FLAG_STRT ((uint32_t)ADC_SR_STRT)
|
|
#define ADC_FLAG_OVR ((uint32_t)ADC_SR_OVR)
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup ADC_channels_type
|
|
* @{
|
|
*/
|
|
#define ALL_CHANNELS ((uint32_t)0x00000001)
|
|
#define REGULAR_CHANNELS ((uint32_t)0x00000002) /*!< reserved for future use */
|
|
#define INJECTED_CHANNELS ((uint32_t)0x00000003) /*!< reserved for future use */
|
|
|
|
#define IS_ADC_CHANNELS_TYPE(CHANNEL_TYPE) (((CHANNEL_TYPE) == ALL_CHANNELS) || \
|
|
((CHANNEL_TYPE) == REGULAR_CHANNELS) || \
|
|
((CHANNEL_TYPE) == INJECTED_CHANNELS))
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup ADC_thresholds
|
|
* @{
|
|
*/
|
|
#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= ((uint32_t)0xFFF))
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup ADC_regular_length
|
|
* @{
|
|
*/
|
|
#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)16)))
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup ADC_regular_rank
|
|
* @{
|
|
*/
|
|
#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= ((uint32_t)1)) && ((RANK) <= ((uint32_t)16)))
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup ADC_regular_discontinuous_mode_number
|
|
* @{
|
|
*/
|
|
#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= ((uint32_t)1)) && ((NUMBER) <= ((uint32_t)8)))
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup ADC_range_verification
|
|
* @{
|
|
*/
|
|
#define IS_ADC_RANGE(RESOLUTION, ADC_VALUE) \
|
|
((((RESOLUTION) == ADC_RESOLUTION12b) && ((ADC_VALUE) <= ((uint32_t)0x0FFF))) || \
|
|
(((RESOLUTION) == ADC_RESOLUTION10b) && ((ADC_VALUE) <= ((uint32_t)0x03FF))) || \
|
|
(((RESOLUTION) == ADC_RESOLUTION8b) && ((ADC_VALUE) <= ((uint32_t)0x00FF))) || \
|
|
(((RESOLUTION) == ADC_RESOLUTION6b) && ((ADC_VALUE) <= ((uint32_t)0x003F))))
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/* Exported macro ------------------------------------------------------------*/
|
|
/**
|
|
* @brief Enable the ADC peripheral.
|
|
* @param __HANDLE__: ADC handle
|
|
* @retval None
|
|
*/
|
|
#define __HAL_ADC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 |= ADC_CR2_ADON)
|
|
|
|
/**
|
|
* @brief Disable the ADC peripheral.
|
|
* @param __HANDLE__: ADC handle
|
|
* @retval None
|
|
*/
|
|
#define __HAL_ADC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= ~ADC_CR2_ADON)
|
|
|
|
/**
|
|
* @brief Set ADC Regular channel sequence length.
|
|
* @param _NbrOfConversion_: Regular channel sequence length.
|
|
* @retval None
|
|
*/
|
|
#define __HAL_ADC_SQR1(_NbrOfConversion_) (((_NbrOfConversion_) - (uint8_t)1) << 20)
|
|
|
|
/**
|
|
* @brief Set the ADC's sample time for channel numbers between 10 and 18.
|
|
* @param _SAMPLETIME_: Sample time parameter.
|
|
* @param _CHANNELNB_: Channel number.
|
|
* @retval None
|
|
*/
|
|
#define __HAL_ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * ((_CHANNELNB_) - 10)))
|
|
|
|
/**
|
|
* @brief Set the ADC's sample time for channel numbers between 0 and 9.
|
|
* @param _SAMPLETIME_: Sample time parameter.
|
|
* @param _CHANNELNB_: Channel number.
|
|
* @retval None
|
|
*/
|
|
#define __HAL_ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * (_CHANNELNB_)))
|
|
|
|
/**
|
|
* @brief Set the selected regular channel rank for rank between 1 and 6.
|
|
* @param _CHANNELNB_: Channel number.
|
|
* @param _RANKNB_: Rank number.
|
|
* @retval None
|
|
*/
|
|
#define __HAL_ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (5 * ((_RANKNB_) - 1)))
|
|
|
|
/**
|
|
* @brief Set the selected regular channel rank for rank between 7 and 12.
|
|
* @param _CHANNELNB_: Channel number.
|
|
* @param _RANKNB_: Rank number.
|
|
* @retval None
|
|
*/
|
|
#define __HAL_ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (5 * ((_RANKNB_) - 7)))
|
|
|
|
/**
|
|
* @brief Set the selected regular channel rank for rank between 13 and 16.
|
|
* @param _CHANNELNB_: Channel number.
|
|
* @param _RANKNB_: Rank number.
|
|
* @retval None
|
|
*/
|
|
#define __HAL_ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (5 * ((_RANKNB_) - 13)))
|
|
|
|
/**
|
|
* @brief Enable ADC continuous conversion mode.
|
|
* @param _CONTINUOUS_MODE_: Continuous mode.
|
|
* @retval None
|
|
*/
|
|
#define __HAL_ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 1)
|
|
|
|
/**
|
|
* @brief Configures the number of discontinuous conversions for the regular group channels.
|
|
* @param _NBR_DISCONTINUOUSCONV_: Number of discontinuous conversions.
|
|
* @retval None
|
|
*/
|
|
#define __HAL_ADC_CR1_DISCONTINUOUS(_NBR_DISCONTINUOUSCONV_) (((_NBR_DISCONTINUOUSCONV_) - 1) << 13)
|
|
|
|
/**
|
|
* @brief Enable ADC scan mode.
|
|
* @param _SCANCONV_MODE_: Scan conversion mode.
|
|
* @retval None
|
|
*/
|
|
#define __HAL_ADC_CR1_SCANCONV(_SCANCONV_MODE_) ((_SCANCONV_MODE_) << 8)
|
|
|
|
/**
|
|
* @brief Enable the ADC end of conversion selection.
|
|
* @param _EOCSelection_MODE_: End of conversion selection mode.
|
|
* @retval None
|
|
*/
|
|
#define __HAL_ADC_CR2_EOCSelection(_EOCSelection_MODE_) ((_EOCSelection_MODE_) << 10)
|
|
|
|
/**
|
|
* @brief Enable the ADC DMA continuous request.
|
|
* @param _DMAContReq_MODE_: DMA continuous request mode.
|
|
* @retval None
|
|
*/
|
|
#define __HAL_ADC_CR2_DMAContReq(_DMAContReq_MODE_) ((_DMAContReq_MODE_) << 9)
|
|
|
|
/**
|
|
* @brief Enable the ADC end of conversion interrupt.
|
|
* @param __HANDLE__: specifies the ADC Handle.
|
|
* @param __INTERRUPT__: ADC Interrupt.
|
|
* @retval None
|
|
*/
|
|
#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) |= (__INTERRUPT__))
|
|
|
|
/**
|
|
* @brief Disable the ADC end of conversion interrupt.
|
|
* @param __HANDLE__: specifies the ADC Handle.
|
|
* @param __INTERRUPT__: ADC interrupt.
|
|
* @retval None
|
|
*/
|
|
#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) &= ~(__INTERRUPT__))
|
|
|
|
/** @brief Check if the specified ADC interrupt source is enabled or disabled.
|
|
* @param __HANDLE__: specifies the ADC Handle.
|
|
* @param __INTERRUPT__: specifies the ADC interrupt source to check.
|
|
* @retval The new state of __IT__ (TRUE or FALSE).
|
|
*/
|
|
#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
|
|
|
/**
|
|
* @brief Clear the ADC's pending flags.
|
|
* @param __HANDLE__: specifies the ADC Handle.
|
|
* @param __FLAG__: ADC flag.
|
|
* @retval None
|
|
*/
|
|
#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) &= ~(__FLAG__))
|
|
|
|
/**
|
|
* @brief Get the selected ADC's flag status.
|
|
* @param __HANDLE__: specifies the ADC Handle.
|
|
* @param __FLAG__: ADC flag.
|
|
* @retval None
|
|
*/
|
|
#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
|
|
|
|
/**
|
|
* @brief Return resolution bits in CR1 register.
|
|
* @param __HANDLE__: ADC handle
|
|
* @retval None
|
|
*/
|
|
#define __HAL_ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CR1) & ADC_CR1_RES)
|
|
|
|
/* Include ADC HAL Extension module */
|
|
#include "stm32f2xx_hal_adc_ex.h"
|
|
|
|
/* Exported functions --------------------------------------------------------*/
|
|
/* Initialization/de-initialization functions ***********************************/
|
|
HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc);
|
|
HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
|
|
void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc);
|
|
void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc);
|
|
|
|
/* I/O operation functions ******************************************************/
|
|
HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc);
|
|
HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc);
|
|
HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
|
|
|
|
HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout);
|
|
|
|
HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc);
|
|
HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc);
|
|
|
|
void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc);
|
|
|
|
HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);
|
|
HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc);
|
|
|
|
uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc);
|
|
|
|
void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc);
|
|
void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc);
|
|
void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc);
|
|
void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
|
|
|
|
/* Peripheral Control functions *************************************************/
|
|
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig);
|
|
HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig);
|
|
|
|
/* Peripheral State functions ***************************************************/
|
|
HAL_ADC_StateTypeDef HAL_ADC_GetState(ADC_HandleTypeDef* hadc);
|
|
uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif /*__STM32F2xx_ADC_H */
|
|
|
|
|
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|