c7404a3ff8
This allows calls to `allocate_memory()` while the VM is running, it will then allocate from the GC heap (unless there is a suitable hole among the supervisor allocations), and when the VM exits and the GC heap is freed, the allocation will be moved to the bottom of the former GC heap and transformed into a proper supervisor allocation. Existing movable allocations will also be moved to defragment the supervisor heap and ensure that the next VM run gets as much memory as possible for the GC heap. By itself this breaks terminalio because it violates the assumption that supervisor_display_move_memory() still has access to an undisturbed heap to copy the tilegrid from. It will work in many cases, but if you're unlucky you will get garbled terminal contents after exiting from the vm run that created the display. This will be fixed in the following commit, which is separate to simplify review.
457 lines
14 KiB
C
457 lines
14 KiB
C
/*
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* This file is part of the MicroPython project, http://micropython.org/
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2017 Scott Shawcroft for Adafruit Industries
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* Copyright (c) 2019 Lucian Copeland for Adafruit Industries
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include <stdint.h>
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#include "supervisor/port.h"
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#include "boards/board.h"
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#include "lib/timeutils/timeutils.h"
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#include "common-hal/microcontroller/Pin.h"
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#if CIRCUITPY_BUSIO
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#include "common-hal/busio/I2C.h"
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#include "common-hal/busio/SPI.h"
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#include "common-hal/busio/UART.h"
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#endif
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#if CIRCUITPY_PULSEIO
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#include "common-hal/pulseio/PulseOut.h"
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#include "common-hal/pulseio/PulseIn.h"
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#endif
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#if CIRCUITPY_PWMIO
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#include "common-hal/pwmio/PWMOut.h"
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#endif
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#if CIRCUITPY_PULSEIO || CIRCUITPY_PWMIO
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#include "timers.h"
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#endif
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#if CIRCUITPY_SDIOIO
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#include "common-hal/sdioio/SDCard.h"
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#endif
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#include "clocks.h"
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#include "gpio.h"
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#include STM32_HAL_H
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void NVIC_SystemReset(void) NORETURN;
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#if (CPY_STM32H7) || (CPY_STM32F7)
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// Device memories must be accessed in order.
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#define DEVICE 2
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// Normal memory can have accesses reorder and prefetched.
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#define NORMAL 0
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// Prevents instruction access.
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#define NO_EXECUTION 1
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#define EXECUTION 0
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// Shareable if the memory system manages coherency.
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#define NOT_SHAREABLE 0
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#define SHAREABLE 1
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#define NOT_CACHEABLE 0
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#define CACHEABLE 1
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#define NOT_BUFFERABLE 0
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#define BUFFERABLE 1
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#define NO_SUBREGIONS 0
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extern uint32_t _ld_stack_top;
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extern uint32_t _ld_d1_ram_bss_start;
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extern uint32_t _ld_d1_ram_bss_size;
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extern uint32_t _ld_d1_ram_data_destination;
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extern uint32_t _ld_d1_ram_data_size;
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extern uint32_t _ld_d1_ram_data_flash_copy;
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extern uint32_t _ld_dtcm_bss_start;
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extern uint32_t _ld_dtcm_bss_size;
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extern uint32_t _ld_dtcm_data_destination;
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extern uint32_t _ld_dtcm_data_size;
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extern uint32_t _ld_dtcm_data_flash_copy;
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extern uint32_t _ld_itcm_destination;
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extern uint32_t _ld_itcm_size;
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extern uint32_t _ld_itcm_flash_copy;
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extern void main(void);
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extern void SystemInit(void);
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// This replaces the Reset_Handler in gcc/startup_*.s, calls SystemInit from system_*.c
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__attribute__((used, naked)) void Reset_Handler(void) {
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__disable_irq();
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__set_MSP((uint32_t) &_ld_stack_top);
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/* Disable MPU */
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ARM_MPU_Disable();
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// Copy all of the itcm code to run from ITCM. Do this while the MPU is disabled because we write
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// protect it.
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for (uint32_t i = 0; i < ((size_t) &_ld_itcm_size) / 4; i++) {
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(&_ld_itcm_destination)[i] = (&_ld_itcm_flash_copy)[i];
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}
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// The first number in RBAR is the region number. When searching for a policy, the region with
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// the highest number wins. If none match, then the default policy set at enable applies.
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// Mark all the flash the same until instructed otherwise.
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MPU->RBAR = ARM_MPU_RBAR(11, 0x08000000U);
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MPU->RASR = ARM_MPU_RASR(EXECUTION, ARM_MPU_AP_FULL, NORMAL, NOT_SHAREABLE, CACHEABLE, BUFFERABLE, NO_SUBREGIONS, CPY_FLASH_REGION_SIZE);
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// This the ITCM. Set it to read-only because we've loaded everything already and it's easy to
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// accidentally write the wrong value to 0x00000000 (aka NULL).
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MPU->RBAR = ARM_MPU_RBAR(12, 0x00000000U);
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MPU->RASR = ARM_MPU_RASR(EXECUTION, ARM_MPU_AP_RO, NORMAL, NOT_SHAREABLE, CACHEABLE, BUFFERABLE, NO_SUBREGIONS, CPY_ITCM_REGION_SIZE);
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// This the DTCM.
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MPU->RBAR = ARM_MPU_RBAR(14, 0x20000000U);
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MPU->RASR = ARM_MPU_RASR(EXECUTION, ARM_MPU_AP_FULL, NORMAL, NOT_SHAREABLE, CACHEABLE, BUFFERABLE, NO_SUBREGIONS, CPY_DTCM_REGION_SIZE);
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// This is AXI SRAM (D1).
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MPU->RBAR = ARM_MPU_RBAR(15, CPY_SRAM_START_ADDR);
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MPU->RASR = ARM_MPU_RASR(EXECUTION, ARM_MPU_AP_FULL, NORMAL, NOT_SHAREABLE, CACHEABLE, BUFFERABLE, CPY_SRAM_SUBMASK, CPY_SRAM_REGION_SIZE);
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/* Enable MPU */
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ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk);
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// Copy all of the data to run from DTCM.
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for (uint32_t i = 0; i < ((size_t) &_ld_dtcm_data_size) / 4; i++) {
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(&_ld_dtcm_data_destination)[i] = (&_ld_dtcm_data_flash_copy)[i];
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}
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// Clear DTCM bss.
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for (uint32_t i = 0; i < ((size_t) &_ld_dtcm_bss_size) / 4; i++) {
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(&_ld_dtcm_bss_start)[i] = 0;
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}
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// Copy all of the data to run from D1 RAM.
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for (uint32_t i = 0; i < ((size_t) &_ld_d1_ram_data_size) / 4; i++) {
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(&_ld_d1_ram_data_destination)[i] = (&_ld_d1_ram_data_flash_copy)[i];
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}
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// Clear D1 RAM bss.
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for (uint32_t i = 0; i < ((size_t) &_ld_d1_ram_bss_size) / 4; i++) {
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(&_ld_d1_ram_bss_start)[i] = 0;
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}
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SystemInit();
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__enable_irq();
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main();
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}
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#endif //end H7 specific code
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// Low power clock variables
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static volatile uint32_t systick_ms;
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static RTC_HandleTypeDef _hrtc;
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#if BOARD_HAS_LOW_SPEED_CRYSTAL
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static uint32_t rtc_clock_frequency = LSE_VALUE;
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#else
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static uint32_t rtc_clock_frequency = LSI_VALUE;
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#endif
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safe_mode_t port_init(void) {
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HAL_Init(); // Turns on SysTick
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__HAL_RCC_SYSCFG_CLK_ENABLE();
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#if (CPY_STM32F4)
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__HAL_RCC_PWR_CLK_ENABLE();
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#endif
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stm32_peripherals_clocks_init();
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stm32_peripherals_gpio_init();
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// RTC oscillator selection is handled in peripherals/<family>/<line>/clocks.c
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__HAL_RCC_RTC_ENABLE();
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_hrtc.Instance = RTC;
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_hrtc.Init.HourFormat = RTC_HOURFORMAT_24;
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// Divide async as little as possible so that we have rtc_clock_frequency count in subseconds.
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// This ensures our timing > 1 second is correct.
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_hrtc.Init.AsynchPrediv = 0x0;
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_hrtc.Init.SynchPrediv = rtc_clock_frequency - 1;
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_hrtc.Init.OutPut = RTC_OUTPUT_DISABLE;
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HAL_RTC_Init(&_hrtc);
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HAL_RTCEx_EnableBypassShadow(&_hrtc);
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HAL_NVIC_EnableIRQ(RTC_Alarm_IRQn);
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// Turn off SysTick
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SysTick->CTRL = 0;
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return NO_SAFE_MODE;
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}
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void HAL_Delay(uint32_t delay_ms) {
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if (SysTick->CTRL != 0) {
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// SysTick is on, so use it
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uint32_t tickstart = systick_ms;
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while (systick_ms - tickstart < delay_ms) {
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}
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} else {
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mp_hal_delay_ms(delay_ms);
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}
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}
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uint32_t HAL_GetTick() {
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if (SysTick->CTRL != 0) {
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return systick_ms;
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} else {
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uint8_t subticks;
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uint32_t result = (uint32_t)port_get_raw_ticks(&subticks);
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return result;
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}
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}
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void SysTick_Handler(void) {
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systick_ms += 1;
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// Read the CTRL register to clear the SysTick interrupt.
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SysTick->CTRL;
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}
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void reset_port(void) {
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reset_all_pins();
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#if CIRCUITPY_BUSIO
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i2c_reset();
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spi_reset();
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uart_reset();
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#endif
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#if CIRCUITPY_SDIOIO
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sdioio_reset();
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#endif
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#if CIRCUITPY_PULSEIO || CIRCUITPY_PWMIO
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timers_reset();
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#endif
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#if CIRCUITPY_PULSEIO
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pulseout_reset();
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pulsein_reset();
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#endif
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#if CIRCUITPY_PWMIO
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pwmout_reset();
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#endif
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}
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void reset_to_bootloader(void) {
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NVIC_SystemReset();
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}
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void reset_cpu(void) {
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NVIC_SystemReset();
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}
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extern uint32_t _ld_heap_start, _ld_heap_end, _ld_stack_top, _ld_stack_bottom;
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uint32_t *port_heap_get_bottom(void) {
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return &_ld_heap_start;
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}
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uint32_t *port_heap_get_top(void) {
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return &_ld_heap_end;
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}
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bool port_has_fixed_stack(void) {
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return false;
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}
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uint32_t *port_stack_get_limit(void) {
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return &_ld_stack_bottom;
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}
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uint32_t *port_stack_get_top(void) {
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return &_ld_stack_top;
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}
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extern uint32_t _ebss;
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// Place the word to save just after our BSS section that gets blanked.
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void port_set_saved_word(uint32_t value) {
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_ebss = value;
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}
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uint32_t port_get_saved_word(void) {
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return _ebss;
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}
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__attribute__((used)) void MemManage_Handler(void)
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{
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reset_into_safe_mode(MEM_MANAGE);
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while (true) {
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asm("nop;");
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}
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}
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__attribute__((used)) void BusFault_Handler(void)
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{
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reset_into_safe_mode(MEM_MANAGE);
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while (true) {
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asm("nop;");
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}
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}
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__attribute__((used)) void UsageFault_Handler(void)
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{
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reset_into_safe_mode(MEM_MANAGE);
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while (true) {
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asm("nop;");
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}
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}
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__attribute__((used)) void HardFault_Handler(void)
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{
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reset_into_safe_mode(HARD_CRASH);
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while (true) {
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asm("nop;");
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}
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}
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// This function is called often for timing so we cache the seconds elapsed computation based on the
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// register value. The STM HAL always does shifts and conversion if we use it directly.
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volatile uint32_t seconds_to_date = 0;
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volatile uint32_t cached_date = 0;
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volatile uint32_t seconds_to_minute = 0;
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volatile uint32_t cached_hours_minutes = 0;
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uint64_t port_get_raw_ticks(uint8_t* subticks) {
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// Disable IRQs to ensure we read all of the RTC registers as close in time as possible. Read
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// SSR twice to make sure we didn't read across a tick.
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__disable_irq();
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uint32_t first_ssr = (uint32_t)(RTC->SSR);
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uint32_t time = (uint32_t)(RTC->TR & RTC_TR_RESERVED_MASK);
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uint32_t date = (uint32_t)(RTC->DR & RTC_DR_RESERVED_MASK);
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uint32_t ssr = (uint32_t)(RTC->SSR);
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while (ssr != first_ssr) {
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first_ssr = ssr;
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time = (uint32_t)(RTC->TR & RTC_TR_RESERVED_MASK);
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date = (uint32_t)(RTC->DR & RTC_DR_RESERVED_MASK);
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ssr = (uint32_t)(RTC->SSR);
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}
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__enable_irq();
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uint32_t subseconds = rtc_clock_frequency - 1 - ssr;
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if (date != cached_date) {
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uint32_t year = (uint8_t)((date & (RTC_DR_YT | RTC_DR_YU)) >> 16U);
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uint8_t month = (uint8_t)((date & (RTC_DR_MT | RTC_DR_MU)) >> 8U);
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uint8_t day = (uint8_t)(date & (RTC_DR_DT | RTC_DR_DU));
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// Add 2000 since the year is only the last two digits.
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year = 2000 + (uint32_t)RTC_Bcd2ToByte(year);
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month = (uint8_t)RTC_Bcd2ToByte(month);
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day = (uint8_t)RTC_Bcd2ToByte(day);
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seconds_to_date = timeutils_seconds_since_2000(year, month, day, 0, 0, 0);
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cached_date = date;
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}
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uint32_t hours_minutes = time & (RTC_TR_HT | RTC_TR_HU | RTC_TR_MNT | RTC_TR_MNU);
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if (hours_minutes != cached_hours_minutes) {
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uint8_t hours = (uint8_t)((time & (RTC_TR_HT | RTC_TR_HU)) >> 16U);
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uint8_t minutes = (uint8_t)((time & (RTC_TR_MNT | RTC_TR_MNU)) >> 8U);
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hours = (uint8_t)RTC_Bcd2ToByte(hours);
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minutes = (uint8_t)RTC_Bcd2ToByte(minutes);
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seconds_to_minute = 60 * (60 * hours + minutes);
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cached_hours_minutes = hours_minutes;
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}
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uint8_t seconds = (uint8_t)(time & (RTC_TR_ST | RTC_TR_SU));
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seconds = (uint8_t)RTC_Bcd2ToByte(seconds);
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if (subticks != NULL) {
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*subticks = subseconds % 32;
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}
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uint64_t raw_ticks = ((uint64_t) 1024) * (seconds_to_date + seconds_to_minute + seconds) + subseconds / 32;
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return raw_ticks;
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}
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void RTC_WKUP_IRQHandler(void) {
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supervisor_tick();
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__HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(&_hrtc, RTC_FLAG_WUTF);
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__HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG();
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}
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volatile bool alarmed_already = false;
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void RTC_Alarm_IRQHandler(void) {
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HAL_RTC_DeactivateAlarm(&_hrtc, RTC_ALARM_A);
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__HAL_RTC_ALARM_EXTI_CLEAR_FLAG();
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__HAL_RTC_ALARM_CLEAR_FLAG(&_hrtc, RTC_FLAG_ALRAF);
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alarmed_already = true;
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}
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// Enable 1/1024 second tick.
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void port_enable_tick(void) {
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HAL_RTCEx_SetWakeUpTimer_IT(&_hrtc, rtc_clock_frequency / 1024 / 2, RTC_WAKEUPCLOCK_RTCCLK_DIV2);
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HAL_NVIC_SetPriority(RTC_WKUP_IRQn, 1, 0U);
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HAL_NVIC_EnableIRQ(RTC_WKUP_IRQn);
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}
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extern volatile uint32_t autoreload_delay_ms;
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// Disable 1/1024 second tick.
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void port_disable_tick(void) {
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HAL_NVIC_DisableIRQ(RTC_WKUP_IRQn);
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HAL_RTCEx_DeactivateWakeUpTimer(&_hrtc);
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}
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void port_interrupt_after_ticks(uint32_t ticks) {
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uint64_t raw_ticks = port_get_raw_ticks(NULL) + ticks;
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RTC_AlarmTypeDef alarm;
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if (ticks > 1024) {
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timeutils_struct_time_t tm;
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timeutils_seconds_since_2000_to_struct_time(raw_ticks / 1024, &tm);
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alarm.AlarmTime.Hours = tm.tm_hour;
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alarm.AlarmTime.Minutes = tm.tm_min;
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alarm.AlarmTime.Seconds = tm.tm_sec;
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alarm.AlarmDateWeekDay = tm.tm_mday;
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// Masking here means that the value is ignored so we set none.
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alarm.AlarmMask = RTC_ALARMMASK_NONE;
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} else {
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// Masking here means that the value is ignored so we set them all. Only the subseconds
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// value matters.
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alarm.AlarmMask = RTC_ALARMMASK_ALL;
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}
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alarm.AlarmTime.SubSeconds = rtc_clock_frequency - 1 -
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((raw_ticks % 1024) * 32);
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alarm.AlarmTime.DayLightSaving = RTC_DAYLIGHTSAVING_NONE;
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alarm.AlarmTime.StoreOperation = RTC_STOREOPERATION_SET;
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// Masking here means that the bits are ignored so we set none of them.
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alarm.AlarmSubSecondMask = RTC_ALARMSUBSECONDMASK_NONE;
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alarm.AlarmDateWeekDaySel = RTC_ALARMDATEWEEKDAYSEL_DATE;
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alarm.Alarm = RTC_ALARM_A;
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HAL_RTC_SetAlarm_IT(&_hrtc, &alarm, RTC_FORMAT_BIN);
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alarmed_already = false;
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}
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void port_sleep_until_interrupt(void) {
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// Clear the FPU interrupt because it can prevent us from sleeping.
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if (__get_FPSCR() & ~(0x9f)) {
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__set_FPSCR(__get_FPSCR() & ~(0x9f));
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|
(void) __get_FPSCR();
|
|
}
|
|
if (alarmed_already) {
|
|
return;
|
|
}
|
|
__WFI();
|
|
}
|
|
|
|
// Required by __libc_init_array in startup code if we are compiling using
|
|
// -nostdlib/-nostartfiles.
|
|
void _init(void)
|
|
{
|
|
|
|
}
|