87 lines
2.9 KiB
C
87 lines
2.9 KiB
C
/*
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* This file is part of the MicroPython project, http://micropython.org/
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2018 Scott Shawcroft for Adafruit Industries
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "clocks.h"
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#include "hpl_gclk_config.h"
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#include "shared-bindings/microcontroller/__init__.h"
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#include "py/runtime.h"
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bool gclk_enabled(uint8_t gclk) {
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return GCLK->GENCTRL[gclk].bit.GENEN;
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}
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void disable_gclk(uint8_t gclk) {
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while ((GCLK->SYNCBUSY.vec.GENCTRL & (1 << gclk)) != 0) {}
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GCLK->GENCTRL[gclk].bit.GENEN = false;
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while ((GCLK->SYNCBUSY.vec.GENCTRL & (1 << gclk)) != 0) {}
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}
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void connect_gclk_to_peripheral(uint8_t gclk, uint8_t peripheral) {
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GCLK->PCHCTRL[peripheral].reg = GCLK_PCHCTRL_CHEN | GCLK_PCHCTRL_GEN(gclk);
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while(GCLK->SYNCBUSY.reg != 0) {}
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}
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void disconnect_gclk_from_peripheral(uint8_t gclk, uint8_t peripheral) {
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GCLK->PCHCTRL[peripheral].reg = 0;
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}
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void enable_clock_generator(uint8_t gclk, uint32_t source, uint16_t divisor) {
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GCLK->GENCTRL[gclk].reg = GCLK_GENCTRL_SRC(source) | GCLK_GENCTRL_DIV(divisor) | GCLK_GENCTRL_GENEN;
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while ((GCLK->SYNCBUSY.vec.GENCTRL & (1 << gclk)) != 0) {}
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}
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void disable_clock_generator(uint8_t gclk) {
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GCLK->GENCTRL[gclk].reg = 0;
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while ((GCLK->SYNCBUSY.vec.GENCTRL & (1 << gclk)) != 0) {}
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}
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bool clock_get_enabled(uint8_t type, uint8_t index) {
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return false;
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}
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bool clock_get_parent(uint8_t type, uint8_t index, uint8_t *p_type, uint8_t *p_index) {
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return false;
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}
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uint32_t clock_get_frequency(uint8_t type, uint8_t index) {
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return 0;
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}
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uint32_t clock_get_calibration(uint8_t type, uint8_t index) {
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return 0;
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}
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int clock_set_calibration(uint8_t type, uint8_t index, uint32_t val) {
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return -2;
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}
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STATIC const mp_rom_map_elem_t samd_clock_global_dict_table[] = {
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};
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MP_DEFINE_CONST_DICT(samd_clock_globals, samd_clock_global_dict_table);
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