5bb8a7a7c6
* Enable dcache for OCRAM where the VM heap lives. * Add CIRCUITPY_SWO_TRACE for pushing program counters out over the SWO pin via the ITM module in the CPU. Exempt some functions from instrumentation to reduce traffic and allow inlining. * Place more functions in ITCM to handle errors using code in RAM-only and speed up CP. * Use SET and CLEAR registers for digitalio. The SDK does read, mask and write. * Switch to 2MiB reserved for CircuitPython code. Up from 1MiB. * Run USB interrupts during flash erase and write. * Allow storage writes from CP if the USB drive is disabled. * Get perf bench tests running on CircuitPython and increase timeouts so it works when instrumentation is active.
107 lines
3.7 KiB
Python
107 lines
3.7 KiB
Python
"""Source this file into gdb `source ../../tools/cortex-m-fault-gdb.py` then run
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`cortex-m-fault` to print basic info about the fault registers."""
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SCS = 0xE000E000
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SCB = SCS + 0x0D00
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CPUID = SCB + 0x000 # (R/ ) CPUID Base Register */
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ICSR = SCB + 0x004 # (R/W) Interrupt Control and State Register */
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VTOR = SCB + 0x008 # (R/W) Vector Table Offset Register */
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AIRCR = SCB + 0x00C # (R/W) Application Interrupt and Reset Control Register */
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SCR = SCB + 0x010 # (R/W) System Control Register */
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CCR = SCB + 0x014 # (R/W) Configuration Control Register */
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SHCSR = SCB + 0x024 # (R/W) System Handler Control and State Register */
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CFSR = SCB + 0x028 # (R/W) Configurable Fault Status Register */
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HFSR = SCB + 0x02C # (R/W) HardFault Status Register */
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DFSR = SCB + 0x030 # (R/W) Debug Fault Status Register */
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MMFAR = SCB + 0x034 # (R/W) MemManage Fault Address Register */
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BFAR = SCB + 0x038 # (R/W) BusFault Address Register */
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AFSR = SCB + 0x03C # (R/W) Auxiliary Fault Status Register */
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PARTS = {0xC27: "Cortex M7"}
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EXCEPTIONS = {
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0: "Thread mode",
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2: "Non Maskable Interrupt",
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3: "Hard Fault",
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4: "MemManage Fault",
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5: "Bus Fault",
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6: "Usage Fault",
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11: "SVCAll",
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14: "PendSV",
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15: "SysTick",
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}
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class CortexMFault(gdb.Command):
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def __init__(self):
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super(CortexMFault, self).__init__("cortex-m-fault", gdb.COMMAND_USER)
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def _read(self, address):
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i = gdb.selected_inferior()
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return i.read_memory(address, 4).cast("I")[0]
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def invoke(self, arg, from_tty):
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cpuid = self._read(CPUID)
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implementer = cpuid >> 24
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if implementer != 0x41:
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raise RuntimeError()
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variant = (cpuid >> 20) & 0xF
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constant = (cpuid >> 16) & 0xF
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if constant != 0xF:
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raise RuntimeError()
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revision = cpuid & 0xF
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part_no = (cpuid >> 4) & 0xFFF
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print(PARTS[part_no])
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icsr = self._read(ICSR)
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if (icsr & (1 << 11)) != 0:
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print("No preempted exceptions")
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else:
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print("Another exception was preempted")
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vectactive = icsr & 0x1FF
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if vectactive != 0:
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if vectactive in EXCEPTIONS:
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print(EXCEPTIONS[vectactive])
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else:
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print(vectactive - 16)
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vtor = self._read(VTOR)
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# print(hex(self._read(SHCSR)))
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cfsr = self._read(CFSR)
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ufsr = cfsr >> 16
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bfsr = (cfsr >> 8) & 0xFF
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mmfsr = cfsr & 0xFF
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print("ufsr", hex(ufsr), "bfsr", hex(bfsr), "mmfsr", hex(mmfsr))
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if (bfsr & (1 << 7)) != 0:
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print("Bad address", hex(self._read(BFAR)))
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if (bfsr & (1 << 3)) != 0:
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print("Unstacking from exception error")
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if (bfsr & (1 << 2)) != 0:
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print("Imprecise data bus error")
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if (bfsr & (1 << 1)) != 0:
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print("Precise data bus error")
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if (bfsr & (1 << 0)) != 0:
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print("Instruction bus error")
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if (mmfsr & (1 << 7)) != 0:
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print("Bad address", hex(self._read(MMFAR)))
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if (mmfsr & (1 << 3)) != 0:
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print("Unstacking from exception error")
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if (mmfsr & (1 << 1)) != 0:
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print("Data access violation")
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if (mmfsr & (1 << 0)) != 0:
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print("Instruction access violation")
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if (ufsr & (1 << 8)) != 0:
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print("Unaligned access")
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if (ufsr & (1 << 0)) != 0:
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print("Undefined instruction")
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hfsr = self._read(HFSR)
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if (hfsr & (1 << 30)) != 0:
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print("Forced hard fault")
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if (hfsr & (1 << 1)) != 0:
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print("Bus fault when reading vector table")
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print("VTOR", hex(vtor))
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CortexMFault()
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