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circuitpython/ports
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Damien George 36211baf0e stm32/boards/LEGO_HUB_NO6: Make all SPI flash transfers use 32-bit addr. 
Signed-off-by: Damien George <damien@micropython.org>
2022-06-02 14:30:51 +10:00
..
bare-arm
bare-arm/mpconfigport.h: Disable remaining optional features.
2021-11-01 14:23:06 +11:00
cc3200
ports: Use default VFS config for import_stat and builtin_open.
2022-05-25 13:04:45 +10:00
esp32
esp32/machine_i2c: Implement write-then-read I2C transfers.
2022-06-01 13:20:30 +10:00
esp8266
ports: Use default VFS config for import_stat and builtin_open.
2022-05-25 13:04:45 +10:00
javascript
ports: Use default VFS config for import_stat and builtin_open.
2022-05-25 13:04:45 +10:00
mimxrt
mimxrt/mphalport: Fix strict aliasing error with unique id.
2022-06-02 12:50:14 +10:00
minimal
ports: Use default VFS config for import_stat and builtin_open.
2022-05-25 13:04:45 +10:00
nrf
ports: Use default VFS config for import_stat and builtin_open.
2022-05-25 13:04:45 +10:00
pic16bit
pic16bit: Make port-specific modules use MP_REGISTER_MODULE.
2022-05-18 20:57:09 +10:00
powerpc
py/builtin: Clean up and simplify import_stat and builtin_open config.
2022-05-25 13:04:45 +10:00
qemu-arm
ports: Use default VFS config for import_stat and builtin_open.
2022-05-25 13:04:45 +10:00
renesas-ra
ports: Use default VFS config for import_stat and builtin_open.
2022-05-25 13:04:45 +10:00
rp2
py/emitinlinethumb: Make ARMv7-M instruction use dynamically selectable.
2022-05-26 11:54:48 +10:00
samd
ports: Use default VFS config for import_stat and builtin_open.
2022-05-25 13:04:45 +10:00
stm32
stm32/boards/LEGO_HUB_NO6: Make all SPI flash transfers use 32-bit addr.
2022-06-02 14:30:51 +10:00
teensy
teensy/mpconfigport.h: Remove obsolete macros.
2022-05-26 11:17:46 +10:00
unix
ports: Use default VFS config for import_stat and builtin_open.
2022-05-25 13:04:45 +10:00
windows
ports: Use default VFS config for import_stat and builtin_open.
2022-05-25 13:04:45 +10:00
zephyr
ports: Use default VFS config for import_stat and builtin_open.
2022-05-25 13:04:45 +10:00