733 lines
21 KiB
C
733 lines
21 KiB
C
// For CircuitPython, use SERCOM settings as prototypes to set
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// the default settings. This file defines these SERCOMs
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//
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// SERCOM0: SPI with hal_spi_m_sync.c driver: spi master synchronous
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// SERCOM1: I2C with hal_i2c_m_sync.c driver: i2c master synchronous
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// SERCOM2: USART with hal_usart_async.c driver: usart asynchronous
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// SERCOM3: SPI with hal_spi_m_dma.c: spi master DMA
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#define PROTOTYPE_SERCOM_SPI_M_SYNC SERCOM0
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#define PROTOTYPE_SERCOM_SPI_M_SYNC_CLOCK_FREQUENCY CONF_GCLK_SERCOM0_CORE_FREQUENCY
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#define PROTOTYPE_SERCOM_I2CM_SYNC SERCOM1
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#define PROTOTYPE_SERCOM_USART_ASYNC SERCOM2
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#define PROTOTYPE_SERCOM_USART_ASYNC_CLOCK_FREQUENCY CONF_GCLK_SERCOM2_CORE_FREQUENCY
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/* Auto-generated config file hpl_sercom_config.h */
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#ifndef HPL_SERCOM_CONFIG_H
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#define HPL_SERCOM_CONFIG_H
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// <<< Use Configuration Wizard in Context Menu >>>
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#include <peripheral_clk_config.h>
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// Enable configuration of module
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#ifndef CONF_SERCOM_0_SPI_ENABLE
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#define CONF_SERCOM_0_SPI_ENABLE 1
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#endif
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// Set module in SPI Master mode
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#ifndef CONF_SERCOM_0_SPI_MODE
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#define CONF_SERCOM_0_SPI_MODE 0x03
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#endif
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// <h> Basic Configuration
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// <q> Receive buffer enable
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// <i> Enable receive buffer to receive data from slave (RXEN)
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// <id> spi_master_rx_enable
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#ifndef CONF_SERCOM_0_SPI_RXEN
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#define CONF_SERCOM_0_SPI_RXEN 0x1
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#endif
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// <o> Character Size
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// <i> Bit size for all characters sent over the SPI bus (CHSIZE)
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// <0x0=>8 bits
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// <0x1=>9 bits
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// <id> spi_master_character_size
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#ifndef CONF_SERCOM_0_SPI_CHSIZE
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#define CONF_SERCOM_0_SPI_CHSIZE 0x0
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#endif
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// <o> Baud rate <1-12000000>
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// <i> The SPI data transfer rate
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// <id> spi_master_baud_rate
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#ifndef CONF_SERCOM_0_SPI_BAUD
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#define CONF_SERCOM_0_SPI_BAUD 50000
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#endif
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// </h>
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// <e> Advanced Configuration
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// <id> spi_master_advanced
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#ifndef CONF_SERCOM_0_SPI_ADVANCED
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#define CONF_SERCOM_0_SPI_ADVANCED 0
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#endif
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// <o> Dummy byte <0x00-0x1ff>
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// <id> spi_master_dummybyte
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// <i> Dummy byte used when reading data from the slave without sending any data
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#ifndef CONF_SERCOM_0_SPI_DUMMYBYTE
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#define CONF_SERCOM_0_SPI_DUMMYBYTE 0x1ff
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#endif
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// <o> Data Order
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// <0=>MSB first
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// <1=>LSB first
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// <i> I least significant or most significant bit is shifted out first (DORD)
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// <id> spi_master_arch_dord
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#ifndef CONF_SERCOM_0_SPI_DORD
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#define CONF_SERCOM_0_SPI_DORD 0x0
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#endif
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// <o> Clock Polarity
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// <0=>SCK is low when idle
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// <1=>SCK is high when idle
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// <i> Determines if the leading edge is rising or falling with a corresponding opposite edge at the trailing edge. (CPOL)
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// <id> spi_master_arch_cpol
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#ifndef CONF_SERCOM_0_SPI_CPOL
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#define CONF_SERCOM_0_SPI_CPOL 0x0
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#endif
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// <o> Clock Phase
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// <0x0=>Sample input on leading edge
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// <0x1=>Sample input on trailing edge
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// <i> Determines if input data is sampled on leading or trailing SCK edge. (CPHA)
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// <id> spi_master_arch_cpha
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#ifndef CONF_SERCOM_0_SPI_CPHA
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#define CONF_SERCOM_0_SPI_CPHA 0x0
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#endif
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// <o> Immediate Buffer Overflow Notification
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// <i> Controls when OVF is asserted (IBON)
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// <0x0=>In data stream
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// <0x1=>On buffer overflow
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// <id> spi_master_arch_ibon
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#ifndef CONF_SERCOM_0_SPI_IBON
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#define CONF_SERCOM_0_SPI_IBON 0x0
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#endif
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// <q> Run in stand-by
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// <i> Module stays active in stand-by sleep mode. (RUNSTDBY)
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// <id> spi_master_arch_runstdby
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#ifndef CONF_SERCOM_0_SPI_RUNSTDBY
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#define CONF_SERCOM_0_SPI_RUNSTDBY 0x0
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#endif
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// <o> Debug Stop Mode
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// <i> Behavior of the baud-rate generator when CPU is halted by external debugger. (DBGSTOP)
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// <0=>Keep running
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// <1=>Halt
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// <id> spi_master_arch_dbgstop
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#ifndef CONF_SERCOM_0_SPI_DBGSTOP
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#define CONF_SERCOM_0_SPI_DBGSTOP 0
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#endif
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// </e>
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// Address mode disabled in master mode
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#ifndef CONF_SERCOM_0_SPI_AMODE_EN
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#define CONF_SERCOM_0_SPI_AMODE_EN 0
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#endif
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#ifndef CONF_SERCOM_0_SPI_AMODE
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#define CONF_SERCOM_0_SPI_AMODE 0
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#endif
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#ifndef CONF_SERCOM_0_SPI_ADDR
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#define CONF_SERCOM_0_SPI_ADDR 0
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#endif
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#ifndef CONF_SERCOM_0_SPI_ADDRMASK
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#define CONF_SERCOM_0_SPI_ADDRMASK 0
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#endif
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#ifndef CONF_SERCOM_0_SPI_SSDE
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#define CONF_SERCOM_0_SPI_SSDE 0
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#endif
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#ifndef CONF_SERCOM_0_SPI_MSSEN
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#define CONF_SERCOM_0_SPI_MSSEN 0x0
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#endif
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#ifndef CONF_SERCOM_0_SPI_PLOADEN
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#define CONF_SERCOM_0_SPI_PLOADEN 0
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#endif
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// <o> Receive Data Pinout
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// <0x0=>PAD[0]
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// <0x1=>PAD[1]
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// <0x2=>PAD[2]
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// <0x3=>PAD[3]
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// <id> spi_master_rxpo
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#ifndef CONF_SERCOM_0_SPI_RXPO
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#define CONF_SERCOM_0_SPI_RXPO 2
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#endif
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// <o> Transmit Data Pinout
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// <0x0=>PAD[0,1]_DO_SCK
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// <0x1=>PAD[2,3]_DO_SCK
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// <0x2=>PAD[3,1]_DO_SCK
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// <0x3=>PAD[0,3]_DO_SCK
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// <id> spi_master_txpo
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#ifndef CONF_SERCOM_0_SPI_TXPO
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#define CONF_SERCOM_0_SPI_TXPO 0
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#endif
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// Calculate baud register value from requested baudrate value
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#ifndef CONF_SERCOM_0_SPI_BAUD_RATE
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#define CONF_SERCOM_0_SPI_BAUD_RATE ((float)CONF_GCLK_SERCOM0_CORE_FREQUENCY / (float)(2 * CONF_SERCOM_0_SPI_BAUD)) - 1
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#endif
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#include <peripheral_clk_config.h>
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#ifndef SERCOM_I2CM_CTRLA_MODE_I2C_MASTER
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#define SERCOM_I2CM_CTRLA_MODE_I2C_MASTER (5 << 2)
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#endif
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#ifndef CONF_SERCOM_1_I2CM_ENABLE
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#define CONF_SERCOM_1_I2CM_ENABLE 1
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#endif
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// <h> Basic
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// <o> I2C Bus clock speed (Hz) <1-400000>
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// <i> I2C Bus clock (SCL) speed measured in Hz
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// <id> i2c_master_baud_rate
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#ifndef CONF_SERCOM_1_I2CM_BAUD
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#define CONF_SERCOM_1_I2CM_BAUD 100000
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#endif
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// </h>
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// <e> Advanced
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// <id> i2c_master_advanced
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#ifndef CONF_SERCOM_1_I2CM_ADVANCED_CONFIG
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#define CONF_SERCOM_1_I2CM_ADVANCED_CONFIG 0
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#endif
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// <o> TRise (ns) <0-300>
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// <i> Determined by the bus impedance, check electric characteristics in the datasheet
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// <i> Standard Fast Mode: typical 215ns, max 300ns
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// <i> Fast Mode +: typical 60ns, max 100ns
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// <i> High Speed Mode: typical 20ns, max 40ns
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// <id> i2c_master_arch_trise
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#ifndef CONF_SERCOM_1_I2CM_TRISE
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#define CONF_SERCOM_1_I2CM_TRISE 215
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#endif
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// <q> Master SCL Low Extended Time-Out (MEXTTOEN)
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// <i> This enables the master SCL low extend time-out
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// <id> i2c_master_arch_mexttoen
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#ifndef CONF_SERCOM_1_I2CM_MEXTTOEN
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#define CONF_SERCOM_1_I2CM_MEXTTOEN 0
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#endif
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// <q> Slave SCL Low Extend Time-Out (SEXTTOEN)
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// <i> Enables the slave SCL low extend time-out. If SCL is cumulatively held low for greater than 25ms from the initial START to a STOP, the slave will release its clock hold if enabled and reset the internal state machine
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// <id> i2c_master_arch_sexttoen
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#ifndef CONF_SERCOM_1_I2CM_SEXTTOEN
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#define CONF_SERCOM_1_I2CM_SEXTTOEN 0
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#endif
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// <q> SCL Low Time-Out (LOWTOUT)
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// <i> Enables SCL low time-out. If SCL is held low for 25ms-35ms, the master will release it's clock hold
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// <id> i2c_master_arch_lowtout
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#ifndef CONF_SERCOM_1_I2CM_LOWTOUT
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#define CONF_SERCOM_1_I2CM_LOWTOUT 0
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#endif
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// <o> Inactive Time-Out (INACTOUT)
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// <0x0=>Disabled
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// <0x1=>5-6 SCL cycle time-out(50-60us)
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// <0x2=>10-11 SCL cycle time-out(100-110us)
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// <0x3=>20-21 SCL cycle time-out(200-210us)
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// <i> Defines if inactivity time-out should be enabled, and how long the time-out should be
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// <id> i2c_master_arch_inactout
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#ifndef CONF_SERCOM_1_I2CM_INACTOUT
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#define CONF_SERCOM_1_I2CM_INACTOUT 0x0
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#endif
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// <o> SDA Hold Time (SDAHOLD)
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// <0=>Disabled
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// <1=>50-100ns hold time
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// <2=>300-600ns hold time
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// <3=>400-800ns hold time
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// <i> Defines the SDA hold time with respect to the negative edge of SCL
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// <id> i2c_master_arch_sdahold
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#ifndef CONF_SERCOM_1_I2CM_SDAHOLD
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#define CONF_SERCOM_1_I2CM_SDAHOLD 0x2
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#endif
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// <q> Run in stand-by
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// <i> Determine if the module shall run in standby sleep mode
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// <id> i2c_master_arch_runstdby
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#ifndef CONF_SERCOM_1_I2CM_RUNSTDBY
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#define CONF_SERCOM_1_I2CM_RUNSTDBY 0
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#endif
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// <o> Debug Stop Mode
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// <i> Behavior of the baud-rate generator when CPU is halted by external debugger.
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// <0=>Keep running
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// <1=>Halt
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// <id> i2c_master_arch_dbgstop
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#ifndef CONF_SERCOM_1_I2CM_DEBUG_STOP_MODE
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#define CONF_SERCOM_1_I2CM_DEBUG_STOP_MODE 0
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#endif
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// </e>
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#ifndef CONF_SERCOM_1_I2CM_SPEED
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#define CONF_SERCOM_1_I2CM_SPEED 0x00 // Speed: Standard/Fast mode
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#endif
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#if CONF_SERCOM_1_I2CM_TRISE < 215 || CONF_SERCOM_1_I2CM_TRISE > 300
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#warning Bad I2C Rise time for Standard/Fast mode, reset to 215ns
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#undef CONF_SERCOM_1_I2CM_TRISE
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#define CONF_SERCOM_1_I2CM_TRISE 215
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#endif
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// gclk_freq - (i2c_scl_freq * 10) - (gclk_freq * i2c_scl_freq * Trise)
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// BAUD + BAUDLOW = --------------------------------------------------------------------
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// i2c_scl_freq
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// BAUD: register value low [7:0]
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// BAUDLOW: register value high [15:8], only used for odd BAUD + BAUDLOW
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#define CONF_SERCOM_1_I2CM_BAUD_BAUDLOW \
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(((CONF_GCLK_SERCOM1_CORE_FREQUENCY - (CONF_SERCOM_1_I2CM_BAUD * 10) \
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- (CONF_SERCOM_1_I2CM_TRISE * (CONF_SERCOM_1_I2CM_BAUD / 100) * (CONF_GCLK_SERCOM1_CORE_FREQUENCY / 10000) \
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/ 1000)) \
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* 10 \
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+ 5) \
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/ (CONF_SERCOM_1_I2CM_BAUD * 10))
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#ifndef CONF_SERCOM_1_I2CM_BAUD_RATE
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#if CONF_SERCOM_1_I2CM_BAUD_BAUDLOW > (0xFF * 2)
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#warning Requested I2C baudrate too low, please check
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#define CONF_SERCOM_1_I2CM_BAUD_RATE 0xFF
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#elif CONF_SERCOM_1_I2CM_BAUD_BAUDLOW <= 1
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#warning Requested I2C baudrate too high, please check
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#define CONF_SERCOM_1_I2CM_BAUD_RATE 1
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#else
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#define CONF_SERCOM_1_I2CM_BAUD_RATE \
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((CONF_SERCOM_1_I2CM_BAUD_BAUDLOW & 0x1) \
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? (CONF_SERCOM_1_I2CM_BAUD_BAUDLOW / 2) + ((CONF_SERCOM_1_I2CM_BAUD_BAUDLOW / 2 + 1) << 8) \
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: (CONF_SERCOM_1_I2CM_BAUD_BAUDLOW / 2))
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#endif
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#endif
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#include <peripheral_clk_config.h>
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#ifndef CONF_SERCOM_2_USART_ENABLE
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#define CONF_SERCOM_2_USART_ENABLE 1
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#endif
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// <h> Basic Configuration
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// <q> Receive buffer enable
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// <i> Enable input buffer in SERCOM module
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// <id> usart_rx_enable
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#ifndef CONF_SERCOM_2_USART_RXEN
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#define CONF_SERCOM_2_USART_RXEN 1
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#endif
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// <q> Transmitt buffer enable
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// <i> Enable output buffer in SERCOM module
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// <id> usart_tx_enable
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#ifndef CONF_SERCOM_2_USART_TXEN
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#define CONF_SERCOM_2_USART_TXEN 1
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#endif
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// <o> Frame parity
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// <0x0=>No parity
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// <0x1=>Even parity
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// <0x2=>Odd parity
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// <i> Parity bit mode for USART frame
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// <id> usart_parity
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#ifndef CONF_SERCOM_2_USART_PARITY
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#define CONF_SERCOM_2_USART_PARITY 0x0
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#endif
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// <o> Character Size
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// <0x0=>8 bits
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// <0x1=>9 bits
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// <0x5=>5 bits
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// <0x6=>6 bits
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// <0x7=>7 bits
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// <i> Data character size in USART frame
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// <id> usart_character_size
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#ifndef CONF_SERCOM_2_USART_CHSIZE
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#define CONF_SERCOM_2_USART_CHSIZE 0x0
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#endif
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// <o> Stop Bit
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// <0=>One stop bit
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// <1=>Two stop bits
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// <i> Number of stop bits in USART frame
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// <id> usart_stop_bit
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#ifndef CONF_SERCOM_2_USART_SBMODE
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#define CONF_SERCOM_2_USART_SBMODE 0
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#endif
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// <o> Baud rate <1-3000000>
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// <i> USART baud rate setting
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// <id> usart_baud_rate
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#ifndef CONF_SERCOM_2_USART_BAUD
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#define CONF_SERCOM_2_USART_BAUD 9600
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#endif
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// </h>
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// <e> Advanced configuration
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// <id> usart_advanced
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#ifndef CONF_SERCOM_2_USART_ADVANCED_CONFIG
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#define CONF_SERCOM_2_USART_ADVANCED_CONFIG 0
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#endif
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// <q> Run in stand-by
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// <i> Keep the module running in standby sleep mode
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// <id> usart_arch_runstdby
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#ifndef CONF_SERCOM_2_USART_RUNSTDBY
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#define CONF_SERCOM_2_USART_RUNSTDBY 0
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#endif
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// <q> Immediate Buffer Overflow Notification
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// <i> Controls when the BUFOVF status bit is asserted
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// <id> usart_arch_ibon
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#ifndef CONF_SERCOM_2_USART_IBON
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#define CONF_SERCOM_2_USART_IBON 0
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#endif
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// <q> Start of Frame Detection Enable
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// <i> Will wake the device from any sleep mode if usart_init and usart_enable was run priort to going to sleep. (receive buffer must be enabled)
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// <id> usart_arch_sfde
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#ifndef CONF_SERCOM_2_USART_SFDE
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#define CONF_SERCOM_2_USART_SFDE 0
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#endif
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// <q> Collision Detection Enable
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// <i> Collision detection enable
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// <id> usart_arch_cloden
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#ifndef CONF_SERCOM_2_USART_CLODEN
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#define CONF_SERCOM_2_USART_CLODEN 0
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#endif
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// <o> Operating Mode
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// <0x0=>USART with external clock
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// <0x1=>USART with internal clock
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// <i> Drive the shift register by an internal clock generated by the baud rate generator or an external clock supplied on the XCK pin.
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// <id> usart_arch_clock_mode
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#ifndef CONF_SERCOM_2_USART_MODE
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#define CONF_SERCOM_2_USART_MODE 0x1
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#endif
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// <o> Sample Rate
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// <0x0=>16x arithmetic
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// <0x1=>16x fractional
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// <0x2=>8x arithmetic
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// <0x3=>8x fractional
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// <0x3=>3x
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// <i> How many over-sampling bits used when samling data state
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// <id> usart_arch_sampr
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#ifndef CONF_SERCOM_2_USART_SAMPR
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#define CONF_SERCOM_2_USART_SAMPR 0x0
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#endif
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// <o> Sample Adjustment
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// <0x0=>7-8-9 (3-4-5 8-bit over-sampling)
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// <0x1=>9-10-11 (4-5-6 8-bit over-sampling)
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// <0x2=>11-12-13 (5-6-7 8-bit over-sampling)
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// <0x3=>13-14-15 (6-7-8 8-bit over-sampling)
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// <i> Adjust which samples to use for data sampling in asynchronous mode
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// <id> usart_arch_sampa
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#ifndef CONF_SERCOM_2_USART_SAMPA
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#define CONF_SERCOM_2_USART_SAMPA 0x0
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#endif
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|
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// <o> Fractional Part <0-7>
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// <i> Fractional part of the baud rate if baud rate generator is in fractional mode
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// <id> usart_arch_fractional
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#ifndef CONF_SERCOM_2_USART_FRACTIONAL
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#define CONF_SERCOM_2_USART_FRACTIONAL 0x0
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#endif
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// <o> Data Order
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// <0=>MSB is transmitted first
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// <1=>LSB is transmitted first
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// <i> Data order of the data bits in the frame
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// <id> usart_arch_dord
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#ifndef CONF_SERCOM_2_USART_DORD
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#define CONF_SERCOM_2_USART_DORD 1
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#endif
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|
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// Does not do anything in UART mode
|
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#define CONF_SERCOM_2_USART_CPOL 0
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|
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// <o> Encoding Format
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// <0=>No encoding
|
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// <1=>IrDA encoded
|
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// <id> usart_arch_enc
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#ifndef CONF_SERCOM_2_USART_ENC
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#define CONF_SERCOM_2_USART_ENC 0
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#endif
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// <o> Debug Stop Mode
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// <i> Behavior of the baud-rate generator when CPU is halted by external debugger.
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// <0=>Keep running
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// <1=>Halt
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// <id> usart_arch_dbgstop
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#ifndef CONF_SERCOM_2_USART_DEBUG_STOP_MODE
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#define CONF_SERCOM_2_USART_DEBUG_STOP_MODE 0
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#endif
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|
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// </e>
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|
|
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#ifndef CONF_SERCOM_2_USART_CMODE
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#define CONF_SERCOM_2_USART_CMODE 0
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#endif
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|
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#ifndef CONF_SERCOM_2_USART_RXPO
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#define CONF_SERCOM_2_USART_RXPO 1 /* RX is on PIN_PA09 */
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#endif
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#ifndef CONF_SERCOM_2_USART_TXPO
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#define CONF_SERCOM_2_USART_TXPO 0 /* TX is on PIN_PA08 */
|
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#endif
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|
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/* Set correct parity settings in register interface based on PARITY setting */
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#if CONF_SERCOM_2_USART_PARITY == 0
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#define CONF_SERCOM_2_USART_PMODE 0
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#define CONF_SERCOM_2_USART_FORM 0
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#else
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#define CONF_SERCOM_2_USART_PMODE CONF_SERCOM_2_USART_PARITY - 1
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#define CONF_SERCOM_2_USART_FORM 1
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#endif
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|
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// Calculate BAUD register value in UART mode
|
|
#if CONF_SERCOM_2_USART_SAMPR == 0
|
|
#ifndef CONF_SERCOM_2_USART_BAUD_RATE
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|
#define CONF_SERCOM_2_USART_BAUD_RATE \
|
|
65536 - ((65536 * 16.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY)
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#endif
|
|
#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH
|
|
#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0
|
|
#endif
|
|
#elif CONF_SERCOM_2_USART_SAMPR == 1
|
|
#ifndef CONF_SERCOM_2_USART_BAUD_RATE
|
|
#define CONF_SERCOM_2_USART_BAUD_RATE \
|
|
((CONF_GCLK_SERCOM2_CORE_FREQUENCY) / (CONF_SERCOM_2_USART_BAUD * 16)) - (CONF_SERCOM_2_USART_FRACTIONAL / 8)
|
|
#endif
|
|
#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH
|
|
#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0
|
|
#endif
|
|
#elif CONF_SERCOM_2_USART_SAMPR == 2
|
|
#ifndef CONF_SERCOM_2_USART_BAUD_RATE
|
|
#define CONF_SERCOM_2_USART_BAUD_RATE \
|
|
65536 - ((65536 * 8.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY)
|
|
#endif
|
|
#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH
|
|
#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0
|
|
#endif
|
|
#elif CONF_SERCOM_2_USART_SAMPR == 3
|
|
#ifndef CONF_SERCOM_2_USART_BAUD_RATE
|
|
#define CONF_SERCOM_2_USART_BAUD_RATE \
|
|
((CONF_GCLK_SERCOM2_CORE_FREQUENCY) / (CONF_SERCOM_2_USART_BAUD * 8)) - (CONF_SERCOM_2_USART_FRACTIONAL / 8)
|
|
#endif
|
|
#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH
|
|
#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0
|
|
#endif
|
|
#elif CONF_SERCOM_2_USART_SAMPR == 4
|
|
#ifndef CONF_SERCOM_2_USART_BAUD_RATE
|
|
#define CONF_SERCOM_2_USART_BAUD_RATE \
|
|
65536 - ((65536 * 3.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY)
|
|
#endif
|
|
#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH
|
|
#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0
|
|
#endif
|
|
#endif
|
|
|
|
#include <peripheral_clk_config.h>
|
|
|
|
// Enable configuration of module
|
|
#ifndef CONF_SERCOM_3_SPI_ENABLE
|
|
#define CONF_SERCOM_3_SPI_ENABLE 1
|
|
#endif
|
|
|
|
// <o> SPI DMA TX Channel <0-32>
|
|
// <i> This defines DMA channel to be used
|
|
// <id> spi_master_dma_tx_channel
|
|
#ifndef CONF_SERCOM_3_SPI_M_DMA_TX_CHANNEL
|
|
#define CONF_SERCOM_3_SPI_M_DMA_TX_CHANNEL 0
|
|
#endif
|
|
|
|
// <e> SPI RX Channel Enable
|
|
// <id> spi_master_rx_channel
|
|
#ifndef CONF_SERCOM_3_SPI_RX_CHANNEL
|
|
#define CONF_SERCOM_3_SPI_RX_CHANNEL 1
|
|
#endif
|
|
|
|
// <o> DMA Channel <0-32>
|
|
// <i> This defines DMA channel to be used
|
|
// <id> spi_master_dma_rx_channel
|
|
#ifndef CONF_SERCOM_3_SPI_M_DMA_RX_CHANNEL
|
|
#define CONF_SERCOM_3_SPI_M_DMA_RX_CHANNEL 1
|
|
#endif
|
|
|
|
// </e>
|
|
|
|
// Set module in SPI Master mode
|
|
#ifndef CONF_SERCOM_3_SPI_MODE
|
|
#define CONF_SERCOM_3_SPI_MODE 0x03
|
|
#endif
|
|
|
|
// <h> Basic Configuration
|
|
|
|
// <q> Receive buffer enable
|
|
// <i> Enable receive buffer to receive data from slave (RXEN)
|
|
// <id> spi_master_rx_enable
|
|
#ifndef CONF_SERCOM_3_SPI_RXEN
|
|
#define CONF_SERCOM_3_SPI_RXEN 0x1
|
|
#endif
|
|
|
|
// <o> Character Size
|
|
// <i> Bit size for all characters sent over the SPI bus (CHSIZE)
|
|
// <0x0=>8 bits
|
|
// <0x1=>9 bits
|
|
// <id> spi_master_character_size
|
|
#ifndef CONF_SERCOM_3_SPI_CHSIZE
|
|
#define CONF_SERCOM_3_SPI_CHSIZE 0x0
|
|
#endif
|
|
|
|
// <o> Baud rate <1-12000000>
|
|
// <i> The SPI data transfer rate
|
|
// <id> spi_master_baud_rate
|
|
#ifndef CONF_SERCOM_3_SPI_BAUD
|
|
#define CONF_SERCOM_3_SPI_BAUD 50000
|
|
#endif
|
|
|
|
// </h>
|
|
|
|
// <e> Advanced Configuration
|
|
// <id> spi_master_advanced
|
|
#ifndef CONF_SERCOM_3_SPI_ADVANCED
|
|
#define CONF_SERCOM_3_SPI_ADVANCED 0
|
|
#endif
|
|
|
|
// <o> Dummy byte <0x00-0x1ff>
|
|
// <id> spi_master_dummybyte
|
|
// <i> Dummy byte used when reading data from the slave without sending any data
|
|
#ifndef CONF_SERCOM_3_SPI_DUMMYBYTE
|
|
#define CONF_SERCOM_3_SPI_DUMMYBYTE 0x1ff
|
|
#endif
|
|
|
|
// <o> Data Order
|
|
// <0=>MSB first
|
|
// <1=>LSB first
|
|
// <i> I least significant or most significant bit is shifted out first (DORD)
|
|
// <id> spi_master_arch_dord
|
|
#ifndef CONF_SERCOM_3_SPI_DORD
|
|
#define CONF_SERCOM_3_SPI_DORD 0x0
|
|
#endif
|
|
|
|
// <o> Clock Polarity
|
|
// <0=>SCK is low when idle
|
|
// <1=>SCK is high when idle
|
|
// <i> Determines if the leading edge is rising or falling with a corresponding opposite edge at the trailing edge. (CPOL)
|
|
// <id> spi_master_arch_cpol
|
|
#ifndef CONF_SERCOM_3_SPI_CPOL
|
|
#define CONF_SERCOM_3_SPI_CPOL 0x0
|
|
#endif
|
|
|
|
// <o> Clock Phase
|
|
// <0x0=>Sample input on leading edge
|
|
// <0x1=>Sample input on trailing edge
|
|
// <i> Determines if input data is sampled on leading or trailing SCK edge. (CPHA)
|
|
// <id> spi_master_arch_cpha
|
|
#ifndef CONF_SERCOM_3_SPI_CPHA
|
|
#define CONF_SERCOM_3_SPI_CPHA 0x0
|
|
#endif
|
|
|
|
// <o> Immediate Buffer Overflow Notification
|
|
// <i> Controls when OVF is asserted (IBON)
|
|
// <0x0=>In data stream
|
|
// <0x1=>On buffer overflow
|
|
// <id> spi_master_arch_ibon
|
|
#ifndef CONF_SERCOM_3_SPI_IBON
|
|
#define CONF_SERCOM_3_SPI_IBON 0x0
|
|
#endif
|
|
|
|
// <q> Run in stand-by
|
|
// <i> Module stays active in stand-by sleep mode. (RUNSTDBY)
|
|
// <id> spi_master_arch_runstdby
|
|
#ifndef CONF_SERCOM_3_SPI_RUNSTDBY
|
|
#define CONF_SERCOM_3_SPI_RUNSTDBY 0x0
|
|
#endif
|
|
|
|
// <o> Debug Stop Mode
|
|
// <i> Behavior of the baud-rate generator when CPU is halted by external debugger. (DBGSTOP)
|
|
// <0=>Keep running
|
|
// <1=>Halt
|
|
// <id> spi_master_arch_dbgstop
|
|
#ifndef CONF_SERCOM_3_SPI_DBGSTOP
|
|
#define CONF_SERCOM_3_SPI_DBGSTOP 0
|
|
#endif
|
|
|
|
// </e>
|
|
|
|
// Address mode disabled in master mode
|
|
#ifndef CONF_SERCOM_3_SPI_AMODE_EN
|
|
#define CONF_SERCOM_3_SPI_AMODE_EN 0
|
|
#endif
|
|
|
|
#ifndef CONF_SERCOM_3_SPI_AMODE
|
|
#define CONF_SERCOM_3_SPI_AMODE 0
|
|
#endif
|
|
|
|
#ifndef CONF_SERCOM_3_SPI_ADDR
|
|
#define CONF_SERCOM_3_SPI_ADDR 0
|
|
#endif
|
|
|
|
#ifndef CONF_SERCOM_3_SPI_ADDRMASK
|
|
#define CONF_SERCOM_3_SPI_ADDRMASK 0
|
|
#endif
|
|
|
|
#ifndef CONF_SERCOM_3_SPI_SSDE
|
|
#define CONF_SERCOM_3_SPI_SSDE 0
|
|
#endif
|
|
|
|
#ifndef CONF_SERCOM_3_SPI_MSSEN
|
|
#define CONF_SERCOM_3_SPI_MSSEN 0x0
|
|
#endif
|
|
|
|
#ifndef CONF_SERCOM_3_SPI_PLOADEN
|
|
#define CONF_SERCOM_3_SPI_PLOADEN 0
|
|
#endif
|
|
|
|
// <o> Receive Data Pinout
|
|
// <0x0=>PAD[0]
|
|
// <0x1=>PAD[1]
|
|
// <0x2=>PAD[2]
|
|
// <0x3=>PAD[3]
|
|
// <id> spi_master_rxpo
|
|
#ifndef CONF_SERCOM_3_SPI_RXPO
|
|
#define CONF_SERCOM_3_SPI_RXPO 0
|
|
#endif
|
|
|
|
// <o> Transmit Data Pinout
|
|
// <0x0=>PAD[0,1]_DO_SCK
|
|
// <0x1=>PAD[2,3]_DO_SCK
|
|
// <0x2=>PAD[3,1]_DO_SCK
|
|
// <0x3=>PAD[0,3]_DO_SCK
|
|
// <id> spi_master_txpo
|
|
#ifndef CONF_SERCOM_3_SPI_TXPO
|
|
#define CONF_SERCOM_3_SPI_TXPO 1
|
|
#endif
|
|
|
|
// Calculate baud register value from requested baudrate value
|
|
#ifndef CONF_SERCOM_3_SPI_BAUD_RATE
|
|
#define CONF_SERCOM_3_SPI_BAUD_RATE ((float)CONF_GCLK_SERCOM3_CORE_FREQUENCY / (float)(2 * CONF_SERCOM_3_SPI_BAUD)) - 1
|
|
#endif
|
|
|
|
// <<< end of configuration section >>>
|
|
|
|
#endif // HPL_SERCOM_CONFIG_H
|