c8437f97ae
The UARTs have no FIFOs, so if interrupts are disabled for more than a character time (10 usec at 1 Mbit/sec) then characters get dropped. The overhead for handling a UART ISR is about 0.5 usec, so even at baud rates of 1 Mbit/sec this only corresponds to about 5% of the CPU. Lower baud rates will have less of an impact.
117 lines
4.4 KiB
C
117 lines
4.4 KiB
C
/*
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* This file is part of the Micro Python project, http://micropython.org/
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2013, 2014 Damien P. George
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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// these states correspond to values from query_irq, enable_irq and disable_irq
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#define IRQ_STATE_DISABLED (0x00000001)
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#define IRQ_STATE_ENABLED (0x00000000)
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static inline mp_uint_t query_irq(void) {
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return __get_PRIMASK();
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}
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// enable_irq and disable_irq are defined inline in mpconfigport.h
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MP_DECLARE_CONST_FUN_OBJ(pyb_wfi_obj);
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MP_DECLARE_CONST_FUN_OBJ(pyb_disable_irq_obj);
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MP_DECLARE_CONST_FUN_OBJ(pyb_enable_irq_obj);
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// IRQ priority definitions.
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//
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// Lower number implies higher interrupt priority.
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//
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// The default priority grouping is set to NVIC_PRIORITYGROUP_4 in the
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// HAL_Init function. This corresponds to 4 bits for the priority field
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// and 0 bits for the sub-priority field (which means that for all intensive
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// purposes that the sub-priorities below are ignored).
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//
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// While a given interrupt is being processed, only higher priority (lower number)
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// interrupts will preempt a given interrupt. If sub-priorities are active
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// then the sub-priority determines the order that pending interrupts of
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// a given priority are executed. This is only meaningful if 2 or more
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// interrupts of the same priority are pending at the same time.
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//
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// The priority of the SysTick timer is determined from the TICK_INT_PRIORITY
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// value which is normally set to 0 in the stm32f4xx_hal_conf.h file.
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//
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// The following interrupts are arranged from highest priority to lowest
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// priority to make it a bit easier to figure out.
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// Priority Sub-Priority
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// -------- ------------
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//#def IRQ_PRI_SYSTICK 0
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//#def IRQ_SUBPRI_SYSTICK 0
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// The UARTs have no FIFOs, so if they don't get serviced quickly then characters
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// get dropped. The handling for each character only consumes about 0.5 usec
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#define IRQ_PRI_UART 1
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#define IRQ_SUBPRI_UART 0
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// Flash IRQ must be higher priority than interrupts of all those components
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// that rely on the flash storage.
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#define IRQ_PRI_FLASH 2
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#define IRQ_SUBPRI_FLASH 0
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// SDIO must be higher priority than DMA for SDIO DMA transfers to work.
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#define IRQ_PRI_SDIO 4
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#define IRQ_SUBPRI_SDIO 0
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// DMA should be higher priority than USB, since USB Mass Storage calls
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// into the sdcard driver which waits for the DMA to complete.
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#define IRQ_PRI_DMA 5
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#define IRQ_SUBPRI_DMA 0
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#define IRQ_PRI_OTG_FS 6
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#define IRQ_SUBPRI_OTG_FS 0
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#define IRQ_PRI_OTG_HS 6
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#define IRQ_SUBPRI_OTG_HS 0
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#define IRQ_PRI_TIM3 6
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#define IRQ_SUBPRI_TIM3 0
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#define IRQ_PRI_TIM5 6
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#define IRQ_SUBPRI_TIM5 0
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#define IRQ_PRI_CAN 7
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#define IRQ_SUBPRI_CAN 0
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// Interrupt priority for non-special timers.
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#define IRQ_PRI_TIMX 14
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#define IRQ_SUBPRI_TIMX 0
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#define IRQ_PRI_EXTINT 15
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#define IRQ_SUBPRI_EXTINT 0
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// PENDSV should be at the lowst priority so that other interrupts complete
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// before exception is raised.
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#define IRQ_PRI_PENDSV 15
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#define IRQ_SUBPRI_PENDSV 0
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#define IRQ_PRI_RTC_WKUP 15
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#define IRQ_SUBPRI_RTC_WKUP 0
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