984 lines
32 KiB
C
984 lines
32 KiB
C
/* generated HAL source file - do not edit */
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#include "hal_data.h"
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/* Macros to tie dynamic ELC links to ADC_TRIGGER_SYNC_ELC option in adc_trigger_t. */
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#define ADC_TRIGGER_ADC0 ADC_TRIGGER_SYNC_ELC
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#define ADC_TRIGGER_ADC0_B ADC_TRIGGER_SYNC_ELC
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#define ADC_TRIGGER_ADC1 ADC_TRIGGER_SYNC_ELC
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#define ADC_TRIGGER_ADC1_B ADC_TRIGGER_SYNC_ELC
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iic_master_instance_ctrl_t g_i2c_master2_ctrl;
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const iic_master_extended_cfg_t g_i2c_master2_extend =
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{ .timeout_mode = IIC_MASTER_TIMEOUT_MODE_SHORT,
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/* Actual calculated bitrate: 98945. Actual calculated duty cycle: 51%. */ .clock_settings.brl_value = 15,
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.clock_settings.brh_value = 16, .clock_settings.cks_value = 4, };
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const i2c_master_cfg_t g_i2c_master2_cfg =
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{ .channel = 2, .rate = I2C_MASTER_RATE_STANDARD, .slave = 0x00, .addr_mode = I2C_MASTER_ADDR_MODE_7BIT,
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#define RA_NOT_DEFINED (1)
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#if (RA_NOT_DEFINED == RA_NOT_DEFINED)
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.p_transfer_tx = NULL,
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#else
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.p_transfer_tx = &RA_NOT_DEFINED,
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#endif
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#if (RA_NOT_DEFINED == RA_NOT_DEFINED)
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.p_transfer_rx = NULL,
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#else
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.p_transfer_rx = &RA_NOT_DEFINED,
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#endif
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#undef RA_NOT_DEFINED
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.p_callback = callback_iic,
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.p_context = NULL,
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#if defined(VECTOR_NUMBER_IIC2_RXI)
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.rxi_irq = VECTOR_NUMBER_IIC2_RXI,
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#else
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.rxi_irq = FSP_INVALID_VECTOR,
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#endif
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#if defined(VECTOR_NUMBER_IIC2_TXI)
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.txi_irq = VECTOR_NUMBER_IIC2_TXI,
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#else
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.txi_irq = FSP_INVALID_VECTOR,
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#endif
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#if defined(VECTOR_NUMBER_IIC2_TEI)
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.tei_irq = VECTOR_NUMBER_IIC2_TEI,
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#else
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.tei_irq = FSP_INVALID_VECTOR,
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#endif
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#if defined(VECTOR_NUMBER_IIC2_ERI)
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.eri_irq = VECTOR_NUMBER_IIC2_ERI,
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#else
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.eri_irq = FSP_INVALID_VECTOR,
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#endif
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.ipl = (12),
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.p_extend = &g_i2c_master2_extend, };
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/* Instance structure to use this module. */
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const i2c_master_instance_t g_i2c_master2 =
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{ .p_ctrl = &g_i2c_master2_ctrl, .p_cfg = &g_i2c_master2_cfg, .p_api = &g_i2c_master_on_iic };
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adc_instance_ctrl_t g_adc1_ctrl;
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const adc_extended_cfg_t g_adc1_cfg_extend =
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{ .add_average_count = ADC_ADD_OFF,
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.clearing = ADC_CLEAR_AFTER_READ_ON,
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.trigger_group_b = ADC_TRIGGER_SYNC_ELC,
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.double_trigger_mode = ADC_DOUBLE_TRIGGER_DISABLED,
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.adc_vref_control = ADC_VREF_CONTROL_VREFH, };
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const adc_cfg_t g_adc1_cfg =
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{ .unit = 1, .mode = ADC_MODE_SINGLE_SCAN, .resolution = ADC_RESOLUTION_12_BIT, .alignment =
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(adc_alignment_t)ADC_ALIGNMENT_RIGHT,
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.trigger = ADC_TRIGGER_SOFTWARE, .p_callback = NULL, .p_context = NULL, .p_extend = &g_adc1_cfg_extend,
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#if defined(VECTOR_NUMBER_ADC1_SCAN_END)
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.scan_end_irq = VECTOR_NUMBER_ADC1_SCAN_END,
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#else
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.scan_end_irq = FSP_INVALID_VECTOR,
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#endif
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.scan_end_ipl = (BSP_IRQ_DISABLED),
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#if defined(VECTOR_NUMBER_ADC1_SCAN_END_B)
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.scan_end_b_irq = VECTOR_NUMBER_ADC1_SCAN_END_B,
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#else
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.scan_end_b_irq = FSP_INVALID_VECTOR,
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#endif
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.scan_end_b_ipl = (BSP_IRQ_DISABLED), };
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const adc_channel_cfg_t g_adc1_channel_cfg =
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{ .scan_mask = 0,
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.scan_mask_group_b = 0,
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.priority_group_a = ADC_GROUP_A_PRIORITY_OFF,
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.add_mask = 0,
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.sample_hold_mask = 0,
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.sample_hold_states = 24, };
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/* Instance structure to use this module. */
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const adc_instance_t g_adc1 =
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{ .p_ctrl = &g_adc1_ctrl, .p_cfg = &g_adc1_cfg, .p_channel_cfg = &g_adc1_channel_cfg, .p_api = &g_adc_on_adc };
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adc_instance_ctrl_t g_adc0_ctrl;
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const adc_extended_cfg_t g_adc0_cfg_extend =
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{ .add_average_count = ADC_ADD_OFF,
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.clearing = ADC_CLEAR_AFTER_READ_ON,
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.trigger_group_b = ADC_TRIGGER_SYNC_ELC,
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.double_trigger_mode = ADC_DOUBLE_TRIGGER_DISABLED,
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.adc_vref_control = ADC_VREF_CONTROL_VREFH, };
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const adc_cfg_t g_adc0_cfg =
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{ .unit = 0, .mode = ADC_MODE_SINGLE_SCAN, .resolution = ADC_RESOLUTION_12_BIT, .alignment =
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(adc_alignment_t)ADC_ALIGNMENT_RIGHT,
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.trigger = ADC_TRIGGER_SOFTWARE, .p_callback = NULL, .p_context = NULL, .p_extend = &g_adc0_cfg_extend,
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#if defined(VECTOR_NUMBER_ADC0_SCAN_END)
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.scan_end_irq = VECTOR_NUMBER_ADC0_SCAN_END,
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#else
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.scan_end_irq = FSP_INVALID_VECTOR,
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#endif
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.scan_end_ipl = (BSP_IRQ_DISABLED),
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#if defined(VECTOR_NUMBER_ADC0_SCAN_END_B)
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.scan_end_b_irq = VECTOR_NUMBER_ADC0_SCAN_END_B,
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#else
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.scan_end_b_irq = FSP_INVALID_VECTOR,
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#endif
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.scan_end_b_ipl = (BSP_IRQ_DISABLED), };
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const adc_channel_cfg_t g_adc0_channel_cfg =
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{ .scan_mask = 0,
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.scan_mask_group_b = 0,
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.priority_group_a = ADC_GROUP_A_PRIORITY_OFF,
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.add_mask = 0,
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.sample_hold_mask = 0,
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.sample_hold_states = 24, };
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/* Instance structure to use this module. */
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const adc_instance_t g_adc0 =
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{ .p_ctrl = &g_adc0_ctrl, .p_cfg = &g_adc0_cfg, .p_channel_cfg = &g_adc0_channel_cfg, .p_api = &g_adc_on_adc };
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lpm_instance_ctrl_t g_lpm0_ctrl;
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const lpm_cfg_t g_lpm0_cfg =
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{ .low_power_mode = LPM_MODE_SLEEP,
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.snooze_cancel_sources = LPM_SNOOZE_CANCEL_SOURCE_NONE,
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.standby_wake_sources = LPM_STANDBY_WAKE_SOURCE_RTCALM | (lpm_standby_wake_source_t)0,
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.snooze_request_source = LPM_SNOOZE_REQUEST_RXD0_FALLING,
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.snooze_end_sources = (lpm_snooze_end_t)0,
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.dtc_state_in_snooze = LPM_SNOOZE_DTC_DISABLE,
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#if BSP_FEATURE_LPM_HAS_SBYCR_OPE
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.output_port_enable = LPM_OUTPUT_PORT_ENABLE_RETAIN,
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#endif
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#if BSP_FEATURE_LPM_HAS_DEEP_STANDBY
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.io_port_state = LPM_IO_PORT_NO_CHANGE,
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.power_supply_state = LPM_POWER_SUPPLY_DEEPCUT0,
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.deep_standby_cancel_source = (lpm_deep_standby_cancel_source_t)0,
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.deep_standby_cancel_edge = (lpm_deep_standby_cancel_edge_t)0,
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#endif
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.p_extend = NULL, };
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const lpm_instance_t g_lpm0 =
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{ .p_api = &g_lpm_on_lpm, .p_ctrl = &g_lpm0_ctrl, .p_cfg = &g_lpm0_cfg };
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dtc_instance_ctrl_t g_transfer3_ctrl;
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transfer_info_t g_transfer3_info =
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{ .dest_addr_mode = TRANSFER_ADDR_MODE_INCREMENTED,
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.repeat_area = TRANSFER_REPEAT_AREA_DESTINATION,
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.irq = TRANSFER_IRQ_END,
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.chain_mode = TRANSFER_CHAIN_MODE_DISABLED,
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.src_addr_mode = TRANSFER_ADDR_MODE_FIXED,
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.size = TRANSFER_SIZE_2_BYTE,
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.mode = TRANSFER_MODE_NORMAL,
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.p_dest = (void *)NULL,
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.p_src = (void const *)NULL,
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.num_blocks = 0,
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.length = 0, };
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const dtc_extended_cfg_t g_transfer3_cfg_extend =
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{ .activation_source = VECTOR_NUMBER_SPI1_RXI, };
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const transfer_cfg_t g_transfer3_cfg =
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{ .p_info = &g_transfer3_info, .p_extend = &g_transfer3_cfg_extend, };
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/* Instance structure to use this module. */
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const transfer_instance_t g_transfer3 =
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{ .p_ctrl = &g_transfer3_ctrl, .p_cfg = &g_transfer3_cfg, .p_api = &g_transfer_on_dtc };
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dtc_instance_ctrl_t g_transfer2_ctrl;
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transfer_info_t g_transfer2_info =
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{ .dest_addr_mode = TRANSFER_ADDR_MODE_FIXED,
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.repeat_area = TRANSFER_REPEAT_AREA_SOURCE,
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.irq = TRANSFER_IRQ_END,
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.chain_mode = TRANSFER_CHAIN_MODE_DISABLED,
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.src_addr_mode = TRANSFER_ADDR_MODE_INCREMENTED,
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.size = TRANSFER_SIZE_2_BYTE,
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.mode = TRANSFER_MODE_NORMAL,
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.p_dest = (void *)NULL,
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.p_src = (void const *)NULL,
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.num_blocks = 0,
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.length = 0, };
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const dtc_extended_cfg_t g_transfer2_cfg_extend =
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{ .activation_source = VECTOR_NUMBER_SPI1_TXI, };
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const transfer_cfg_t g_transfer2_cfg =
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{ .p_info = &g_transfer2_info, .p_extend = &g_transfer2_cfg_extend, };
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/* Instance structure to use this module. */
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const transfer_instance_t g_transfer2 =
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{ .p_ctrl = &g_transfer2_ctrl, .p_cfg = &g_transfer2_cfg, .p_api = &g_transfer_on_dtc };
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spi_instance_ctrl_t g_spi1_ctrl;
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/** SPI extended configuration for SPI HAL driver */
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const spi_extended_cfg_t g_spi1_ext_cfg =
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{ .spi_clksyn = SPI_SSL_MODE_CLK_SYN,
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.spi_comm = SPI_COMMUNICATION_FULL_DUPLEX,
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.ssl_polarity = SPI_SSLP_LOW,
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.ssl_select = SPI_SSL_SELECT_SSL0,
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.mosi_idle = SPI_MOSI_IDLE_VALUE_FIXING_DISABLE,
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.parity = SPI_PARITY_MODE_DISABLE,
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.byte_swap = SPI_BYTE_SWAP_DISABLE,
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.spck_div =
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{
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/* Actual calculated bitrate: 15000000. */ .spbr = 3,
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.brdv = 0
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},
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.spck_delay = SPI_DELAY_COUNT_1,
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.ssl_negation_delay = SPI_DELAY_COUNT_1,
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.next_access_delay = SPI_DELAY_COUNT_1 };
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/** SPI configuration for SPI HAL driver */
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const spi_cfg_t g_spi1_cfg =
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{ .channel = 1,
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#if defined(VECTOR_NUMBER_SPI1_RXI)
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.rxi_irq = VECTOR_NUMBER_SPI1_RXI,
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#else
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.rxi_irq = FSP_INVALID_VECTOR,
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#endif
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#if defined(VECTOR_NUMBER_SPI1_TXI)
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.txi_irq = VECTOR_NUMBER_SPI1_TXI,
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#else
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.txi_irq = FSP_INVALID_VECTOR,
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#endif
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#if defined(VECTOR_NUMBER_SPI1_TEI)
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.tei_irq = VECTOR_NUMBER_SPI1_TEI,
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#else
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.tei_irq = FSP_INVALID_VECTOR,
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#endif
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#if defined(VECTOR_NUMBER_SPI1_ERI)
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.eri_irq = VECTOR_NUMBER_SPI1_ERI,
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#else
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.eri_irq = FSP_INVALID_VECTOR,
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#endif
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.rxi_ipl = (12),
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.txi_ipl = (12),
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.tei_ipl = (12),
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.eri_ipl = (12),
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.operating_mode = SPI_MODE_MASTER,
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.clk_phase = SPI_CLK_PHASE_EDGE_ODD,
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.clk_polarity = SPI_CLK_POLARITY_LOW,
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.mode_fault = SPI_MODE_FAULT_ERROR_DISABLE,
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.bit_order = SPI_BIT_ORDER_MSB_FIRST,
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.p_transfer_tx = g_spi1_P_TRANSFER_TX,
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.p_transfer_rx = g_spi1_P_TRANSFER_RX,
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.p_callback = spi_callback,
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.p_context = NULL,
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.p_extend = (void *)&g_spi1_ext_cfg, };
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/* Instance structure to use this module. */
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const spi_instance_t g_spi1 =
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{ .p_ctrl = &g_spi1_ctrl, .p_cfg = &g_spi1_cfg, .p_api = &g_spi_on_spi };
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dtc_instance_ctrl_t g_transfer1_ctrl;
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transfer_info_t g_transfer1_info =
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{ .dest_addr_mode = TRANSFER_ADDR_MODE_INCREMENTED,
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.repeat_area = TRANSFER_REPEAT_AREA_DESTINATION,
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.irq = TRANSFER_IRQ_END,
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.chain_mode = TRANSFER_CHAIN_MODE_DISABLED,
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.src_addr_mode = TRANSFER_ADDR_MODE_FIXED,
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.size = TRANSFER_SIZE_2_BYTE,
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.mode = TRANSFER_MODE_NORMAL,
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.p_dest = (void *)NULL,
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.p_src = (void const *)NULL,
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.num_blocks = 0,
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.length = 0, };
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const dtc_extended_cfg_t g_transfer1_cfg_extend =
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{ .activation_source = VECTOR_NUMBER_SPI0_RXI, };
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const transfer_cfg_t g_transfer1_cfg =
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{ .p_info = &g_transfer1_info, .p_extend = &g_transfer1_cfg_extend, };
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/* Instance structure to use this module. */
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const transfer_instance_t g_transfer1 =
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{ .p_ctrl = &g_transfer1_ctrl, .p_cfg = &g_transfer1_cfg, .p_api = &g_transfer_on_dtc };
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dtc_instance_ctrl_t g_transfer0_ctrl;
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transfer_info_t g_transfer0_info =
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{ .dest_addr_mode = TRANSFER_ADDR_MODE_FIXED,
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.repeat_area = TRANSFER_REPEAT_AREA_SOURCE,
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.irq = TRANSFER_IRQ_END,
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.chain_mode = TRANSFER_CHAIN_MODE_DISABLED,
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.src_addr_mode = TRANSFER_ADDR_MODE_INCREMENTED,
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.size = TRANSFER_SIZE_2_BYTE,
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.mode = TRANSFER_MODE_NORMAL,
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.p_dest = (void *)NULL,
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.p_src = (void const *)NULL,
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.num_blocks = 0,
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.length = 0, };
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const dtc_extended_cfg_t g_transfer0_cfg_extend =
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{ .activation_source = VECTOR_NUMBER_SPI0_TXI, };
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const transfer_cfg_t g_transfer0_cfg =
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{ .p_info = &g_transfer0_info, .p_extend = &g_transfer0_cfg_extend, };
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/* Instance structure to use this module. */
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const transfer_instance_t g_transfer0 =
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{ .p_ctrl = &g_transfer0_ctrl, .p_cfg = &g_transfer0_cfg, .p_api = &g_transfer_on_dtc };
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spi_instance_ctrl_t g_spi0_ctrl;
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/** SPI extended configuration for SPI HAL driver */
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const spi_extended_cfg_t g_spi0_ext_cfg =
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{ .spi_clksyn = SPI_SSL_MODE_CLK_SYN,
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.spi_comm = SPI_COMMUNICATION_FULL_DUPLEX,
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.ssl_polarity = SPI_SSLP_LOW,
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.ssl_select = SPI_SSL_SELECT_SSL0,
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.mosi_idle = SPI_MOSI_IDLE_VALUE_FIXING_DISABLE,
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.parity = SPI_PARITY_MODE_DISABLE,
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.byte_swap = SPI_BYTE_SWAP_DISABLE,
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.spck_div =
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{
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/* Actual calculated bitrate: 15000000. */ .spbr = 3,
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.brdv = 0
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},
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.spck_delay = SPI_DELAY_COUNT_1,
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.ssl_negation_delay = SPI_DELAY_COUNT_1,
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.next_access_delay = SPI_DELAY_COUNT_1 };
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/** SPI configuration for SPI HAL driver */
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const spi_cfg_t g_spi0_cfg =
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{ .channel = 0,
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#if defined(VECTOR_NUMBER_SPI0_RXI)
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.rxi_irq = VECTOR_NUMBER_SPI0_RXI,
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#else
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.rxi_irq = FSP_INVALID_VECTOR,
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#endif
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#if defined(VECTOR_NUMBER_SPI0_TXI)
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.txi_irq = VECTOR_NUMBER_SPI0_TXI,
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#else
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.txi_irq = FSP_INVALID_VECTOR,
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#endif
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#if defined(VECTOR_NUMBER_SPI0_TEI)
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.tei_irq = VECTOR_NUMBER_SPI0_TEI,
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#else
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.tei_irq = FSP_INVALID_VECTOR,
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#endif
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#if defined(VECTOR_NUMBER_SPI0_ERI)
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.eri_irq = VECTOR_NUMBER_SPI0_ERI,
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#else
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.eri_irq = FSP_INVALID_VECTOR,
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#endif
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.rxi_ipl = (12),
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.txi_ipl = (12),
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.tei_ipl = (12),
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.eri_ipl = (12),
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.operating_mode = SPI_MODE_MASTER,
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.clk_phase = SPI_CLK_PHASE_EDGE_ODD,
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.clk_polarity = SPI_CLK_POLARITY_LOW,
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.mode_fault = SPI_MODE_FAULT_ERROR_DISABLE,
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.bit_order = SPI_BIT_ORDER_MSB_FIRST,
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.p_transfer_tx = g_spi0_P_TRANSFER_TX,
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.p_transfer_rx = g_spi0_P_TRANSFER_RX,
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.p_callback = spi_callback,
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.p_context = NULL,
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.p_extend = (void *)&g_spi0_ext_cfg, };
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/* Instance structure to use this module. */
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const spi_instance_t g_spi0 =
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{ .p_ctrl = &g_spi0_ctrl, .p_cfg = &g_spi0_cfg, .p_api = &g_spi_on_spi };
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icu_instance_ctrl_t g_external_irq15_ctrl;
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const external_irq_cfg_t g_external_irq15_cfg =
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{ .channel = 15,
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.trigger = EXTERNAL_IRQ_TRIG_RISING,
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.filter_enable = false,
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.pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64,
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.p_callback = callback_icu,
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.p_context = NULL,
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.p_extend = NULL,
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.ipl = (12),
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#if defined(VECTOR_NUMBER_ICU_IRQ15)
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.irq = VECTOR_NUMBER_ICU_IRQ15,
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#else
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.irq = FSP_INVALID_VECTOR,
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#endif
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};
|
|
/* Instance structure to use this module. */
|
|
const external_irq_instance_t g_external_irq15 =
|
|
{ .p_ctrl = &g_external_irq15_ctrl, .p_cfg = &g_external_irq15_cfg, .p_api = &g_external_irq_on_icu };
|
|
icu_instance_ctrl_t g_external_irq14_ctrl;
|
|
const external_irq_cfg_t g_external_irq14_cfg =
|
|
{ .channel = 14,
|
|
.trigger = EXTERNAL_IRQ_TRIG_RISING,
|
|
.filter_enable = false,
|
|
.pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64,
|
|
.p_callback = callback_icu,
|
|
.p_context = NULL,
|
|
.p_extend = NULL,
|
|
.ipl = (12),
|
|
#if defined(VECTOR_NUMBER_ICU_IRQ14)
|
|
.irq = VECTOR_NUMBER_ICU_IRQ14,
|
|
#else
|
|
.irq = FSP_INVALID_VECTOR,
|
|
#endif
|
|
};
|
|
/* Instance structure to use this module. */
|
|
const external_irq_instance_t g_external_irq14 =
|
|
{ .p_ctrl = &g_external_irq14_ctrl, .p_cfg = &g_external_irq14_cfg, .p_api = &g_external_irq_on_icu };
|
|
icu_instance_ctrl_t g_external_irq13_ctrl;
|
|
const external_irq_cfg_t g_external_irq13_cfg =
|
|
{ .channel = 13,
|
|
.trigger = EXTERNAL_IRQ_TRIG_RISING,
|
|
.filter_enable = false,
|
|
.pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64,
|
|
.p_callback = callback_icu,
|
|
.p_context = NULL,
|
|
.p_extend = NULL,
|
|
.ipl = (12),
|
|
#if defined(VECTOR_NUMBER_ICU_IRQ13)
|
|
.irq = VECTOR_NUMBER_ICU_IRQ13,
|
|
#else
|
|
.irq = FSP_INVALID_VECTOR,
|
|
#endif
|
|
};
|
|
/* Instance structure to use this module. */
|
|
const external_irq_instance_t g_external_irq13 =
|
|
{ .p_ctrl = &g_external_irq13_ctrl, .p_cfg = &g_external_irq13_cfg, .p_api = &g_external_irq_on_icu };
|
|
icu_instance_ctrl_t g_external_irq12_ctrl;
|
|
const external_irq_cfg_t g_external_irq12_cfg =
|
|
{ .channel = 12,
|
|
.trigger = EXTERNAL_IRQ_TRIG_RISING,
|
|
.filter_enable = false,
|
|
.pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64,
|
|
.p_callback = callback_icu,
|
|
.p_context = NULL,
|
|
.p_extend = NULL,
|
|
.ipl = (12),
|
|
#if defined(VECTOR_NUMBER_ICU_IRQ12)
|
|
.irq = VECTOR_NUMBER_ICU_IRQ12,
|
|
#else
|
|
.irq = FSP_INVALID_VECTOR,
|
|
#endif
|
|
};
|
|
/* Instance structure to use this module. */
|
|
const external_irq_instance_t g_external_irq12 =
|
|
{ .p_ctrl = &g_external_irq12_ctrl, .p_cfg = &g_external_irq12_cfg, .p_api = &g_external_irq_on_icu };
|
|
icu_instance_ctrl_t g_external_irq11_ctrl;
|
|
const external_irq_cfg_t g_external_irq11_cfg =
|
|
{ .channel = 11,
|
|
.trigger = EXTERNAL_IRQ_TRIG_RISING,
|
|
.filter_enable = false,
|
|
.pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64,
|
|
.p_callback = callback_icu,
|
|
.p_context = NULL,
|
|
.p_extend = NULL,
|
|
.ipl = (12),
|
|
#if defined(VECTOR_NUMBER_ICU_IRQ11)
|
|
.irq = VECTOR_NUMBER_ICU_IRQ11,
|
|
#else
|
|
.irq = FSP_INVALID_VECTOR,
|
|
#endif
|
|
};
|
|
/* Instance structure to use this module. */
|
|
const external_irq_instance_t g_external_irq11 =
|
|
{ .p_ctrl = &g_external_irq11_ctrl, .p_cfg = &g_external_irq11_cfg, .p_api = &g_external_irq_on_icu };
|
|
icu_instance_ctrl_t g_external_irq10_ctrl;
|
|
const external_irq_cfg_t g_external_irq10_cfg =
|
|
{ .channel = 10,
|
|
.trigger = EXTERNAL_IRQ_TRIG_RISING,
|
|
.filter_enable = false,
|
|
.pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64,
|
|
.p_callback = callback_icu,
|
|
.p_context = NULL,
|
|
.p_extend = NULL,
|
|
.ipl = (12),
|
|
#if defined(VECTOR_NUMBER_ICU_IRQ10)
|
|
.irq = VECTOR_NUMBER_ICU_IRQ10,
|
|
#else
|
|
.irq = FSP_INVALID_VECTOR,
|
|
#endif
|
|
};
|
|
/* Instance structure to use this module. */
|
|
const external_irq_instance_t g_external_irq10 =
|
|
{ .p_ctrl = &g_external_irq10_ctrl, .p_cfg = &g_external_irq10_cfg, .p_api = &g_external_irq_on_icu };
|
|
icu_instance_ctrl_t g_external_irq9_ctrl;
|
|
const external_irq_cfg_t g_external_irq9_cfg =
|
|
{ .channel = 9,
|
|
.trigger = EXTERNAL_IRQ_TRIG_RISING,
|
|
.filter_enable = false,
|
|
.pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64,
|
|
.p_callback = callback_icu,
|
|
.p_context = NULL,
|
|
.p_extend = NULL,
|
|
.ipl = (12),
|
|
#if defined(VECTOR_NUMBER_ICU_IRQ9)
|
|
.irq = VECTOR_NUMBER_ICU_IRQ9,
|
|
#else
|
|
.irq = FSP_INVALID_VECTOR,
|
|
#endif
|
|
};
|
|
/* Instance structure to use this module. */
|
|
const external_irq_instance_t g_external_irq9 =
|
|
{ .p_ctrl = &g_external_irq9_ctrl, .p_cfg = &g_external_irq9_cfg, .p_api = &g_external_irq_on_icu };
|
|
icu_instance_ctrl_t g_external_irq8_ctrl;
|
|
const external_irq_cfg_t g_external_irq8_cfg =
|
|
{ .channel = 8,
|
|
.trigger = EXTERNAL_IRQ_TRIG_RISING,
|
|
.filter_enable = false,
|
|
.pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64,
|
|
.p_callback = callback_icu,
|
|
.p_context = NULL,
|
|
.p_extend = NULL,
|
|
.ipl = (12),
|
|
#if defined(VECTOR_NUMBER_ICU_IRQ8)
|
|
.irq = VECTOR_NUMBER_ICU_IRQ8,
|
|
#else
|
|
.irq = FSP_INVALID_VECTOR,
|
|
#endif
|
|
};
|
|
/* Instance structure to use this module. */
|
|
const external_irq_instance_t g_external_irq8 =
|
|
{ .p_ctrl = &g_external_irq8_ctrl, .p_cfg = &g_external_irq8_cfg, .p_api = &g_external_irq_on_icu };
|
|
icu_instance_ctrl_t g_external_irq7_ctrl;
|
|
const external_irq_cfg_t g_external_irq7_cfg =
|
|
{ .channel = 7,
|
|
.trigger = EXTERNAL_IRQ_TRIG_RISING,
|
|
.filter_enable = false,
|
|
.pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64,
|
|
.p_callback = callback_icu,
|
|
.p_context = NULL,
|
|
.p_extend = NULL,
|
|
.ipl = (12),
|
|
#if defined(VECTOR_NUMBER_ICU_IRQ7)
|
|
.irq = VECTOR_NUMBER_ICU_IRQ7,
|
|
#else
|
|
.irq = FSP_INVALID_VECTOR,
|
|
#endif
|
|
};
|
|
/* Instance structure to use this module. */
|
|
const external_irq_instance_t g_external_irq7 =
|
|
{ .p_ctrl = &g_external_irq7_ctrl, .p_cfg = &g_external_irq7_cfg, .p_api = &g_external_irq_on_icu };
|
|
icu_instance_ctrl_t g_external_irq6_ctrl;
|
|
const external_irq_cfg_t g_external_irq6_cfg =
|
|
{ .channel = 6,
|
|
.trigger = EXTERNAL_IRQ_TRIG_RISING,
|
|
.filter_enable = false,
|
|
.pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64,
|
|
.p_callback = callback_icu,
|
|
.p_context = NULL,
|
|
.p_extend = NULL,
|
|
.ipl = (12),
|
|
#if defined(VECTOR_NUMBER_ICU_IRQ6)
|
|
.irq = VECTOR_NUMBER_ICU_IRQ6,
|
|
#else
|
|
.irq = FSP_INVALID_VECTOR,
|
|
#endif
|
|
};
|
|
/* Instance structure to use this module. */
|
|
const external_irq_instance_t g_external_irq6 =
|
|
{ .p_ctrl = &g_external_irq6_ctrl, .p_cfg = &g_external_irq6_cfg, .p_api = &g_external_irq_on_icu };
|
|
icu_instance_ctrl_t g_external_irq5_ctrl;
|
|
const external_irq_cfg_t g_external_irq5_cfg =
|
|
{ .channel = 5,
|
|
.trigger = EXTERNAL_IRQ_TRIG_RISING,
|
|
.filter_enable = false,
|
|
.pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64,
|
|
.p_callback = callback_icu,
|
|
.p_context = NULL,
|
|
.p_extend = NULL,
|
|
.ipl = (12),
|
|
#if defined(VECTOR_NUMBER_ICU_IRQ5)
|
|
.irq = VECTOR_NUMBER_ICU_IRQ5,
|
|
#else
|
|
.irq = FSP_INVALID_VECTOR,
|
|
#endif
|
|
};
|
|
/* Instance structure to use this module. */
|
|
const external_irq_instance_t g_external_irq5 =
|
|
{ .p_ctrl = &g_external_irq5_ctrl, .p_cfg = &g_external_irq5_cfg, .p_api = &g_external_irq_on_icu };
|
|
icu_instance_ctrl_t g_external_irq4_ctrl;
|
|
const external_irq_cfg_t g_external_irq4_cfg =
|
|
{ .channel = 4,
|
|
.trigger = EXTERNAL_IRQ_TRIG_RISING,
|
|
.filter_enable = false,
|
|
.pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64,
|
|
.p_callback = callback_icu,
|
|
.p_context = NULL,
|
|
.p_extend = NULL,
|
|
.ipl = (12),
|
|
#if defined(VECTOR_NUMBER_ICU_IRQ4)
|
|
.irq = VECTOR_NUMBER_ICU_IRQ4,
|
|
#else
|
|
.irq = FSP_INVALID_VECTOR,
|
|
#endif
|
|
};
|
|
/* Instance structure to use this module. */
|
|
const external_irq_instance_t g_external_irq4 =
|
|
{ .p_ctrl = &g_external_irq4_ctrl, .p_cfg = &g_external_irq4_cfg, .p_api = &g_external_irq_on_icu };
|
|
icu_instance_ctrl_t g_external_irq3_ctrl;
|
|
const external_irq_cfg_t g_external_irq3_cfg =
|
|
{ .channel = 3,
|
|
.trigger = EXTERNAL_IRQ_TRIG_RISING,
|
|
.filter_enable = false,
|
|
.pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64,
|
|
.p_callback = callback_icu,
|
|
.p_context = NULL,
|
|
.p_extend = NULL,
|
|
.ipl = (12),
|
|
#if defined(VECTOR_NUMBER_ICU_IRQ3)
|
|
.irq = VECTOR_NUMBER_ICU_IRQ3,
|
|
#else
|
|
.irq = FSP_INVALID_VECTOR,
|
|
#endif
|
|
};
|
|
/* Instance structure to use this module. */
|
|
const external_irq_instance_t g_external_irq3 =
|
|
{ .p_ctrl = &g_external_irq3_ctrl, .p_cfg = &g_external_irq3_cfg, .p_api = &g_external_irq_on_icu };
|
|
icu_instance_ctrl_t g_external_irq2_ctrl;
|
|
const external_irq_cfg_t g_external_irq2_cfg =
|
|
{ .channel = 2,
|
|
.trigger = EXTERNAL_IRQ_TRIG_RISING,
|
|
.filter_enable = false,
|
|
.pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64,
|
|
.p_callback = callback_icu,
|
|
.p_context = NULL,
|
|
.p_extend = NULL,
|
|
.ipl = (12),
|
|
#if defined(VECTOR_NUMBER_ICU_IRQ2)
|
|
.irq = VECTOR_NUMBER_ICU_IRQ2,
|
|
#else
|
|
.irq = FSP_INVALID_VECTOR,
|
|
#endif
|
|
};
|
|
/* Instance structure to use this module. */
|
|
const external_irq_instance_t g_external_irq2 =
|
|
{ .p_ctrl = &g_external_irq2_ctrl, .p_cfg = &g_external_irq2_cfg, .p_api = &g_external_irq_on_icu };
|
|
icu_instance_ctrl_t g_external_irq1_ctrl;
|
|
const external_irq_cfg_t g_external_irq1_cfg =
|
|
{ .channel = 1,
|
|
.trigger = EXTERNAL_IRQ_TRIG_RISING,
|
|
.filter_enable = false,
|
|
.pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64,
|
|
.p_callback = callback_icu,
|
|
.p_context = NULL,
|
|
.p_extend = NULL,
|
|
.ipl = (12),
|
|
#if defined(VECTOR_NUMBER_ICU_IRQ1)
|
|
.irq = VECTOR_NUMBER_ICU_IRQ1,
|
|
#else
|
|
.irq = FSP_INVALID_VECTOR,
|
|
#endif
|
|
};
|
|
/* Instance structure to use this module. */
|
|
const external_irq_instance_t g_external_irq1 =
|
|
{ .p_ctrl = &g_external_irq1_ctrl, .p_cfg = &g_external_irq1_cfg, .p_api = &g_external_irq_on_icu };
|
|
icu_instance_ctrl_t g_external_irq0_ctrl;
|
|
const external_irq_cfg_t g_external_irq0_cfg =
|
|
{ .channel = 0,
|
|
.trigger = EXTERNAL_IRQ_TRIG_RISING,
|
|
.filter_enable = false,
|
|
.pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64,
|
|
.p_callback = callback_icu,
|
|
.p_context = NULL,
|
|
.p_extend = NULL,
|
|
.ipl = (12),
|
|
#if defined(VECTOR_NUMBER_ICU_IRQ0)
|
|
.irq = VECTOR_NUMBER_ICU_IRQ0,
|
|
#else
|
|
.irq = FSP_INVALID_VECTOR,
|
|
#endif
|
|
};
|
|
/* Instance structure to use this module. */
|
|
const external_irq_instance_t g_external_irq0 =
|
|
{ .p_ctrl = &g_external_irq0_ctrl, .p_cfg = &g_external_irq0_cfg, .p_api = &g_external_irq_on_icu };
|
|
agt_instance_ctrl_t g_timer1_ctrl;
|
|
const agt_extended_cfg_t g_timer1_extend =
|
|
{ .count_source = AGT_CLOCK_PCLKB,
|
|
.agto = AGT_PIN_CFG_DISABLED,
|
|
.agtoa = AGT_PIN_CFG_DISABLED,
|
|
.agtob = AGT_PIN_CFG_DISABLED,
|
|
.measurement_mode = AGT_MEASURE_DISABLED,
|
|
.agtio_filter = AGT_AGTIO_FILTER_NONE,
|
|
.enable_pin = AGT_ENABLE_PIN_NOT_USED,
|
|
.trigger_edge = AGT_TRIGGER_EDGE_RISING, };
|
|
const timer_cfg_t g_timer1_cfg =
|
|
{ .mode = TIMER_MODE_PERIODIC,
|
|
/* Actual period: 0.0010922666666666667 seconds. Actual duty: 50%. */ .period_counts = 0x10000,
|
|
.duty_cycle_counts = 0x8000, .source_div = (timer_source_div_t)0, .channel = 0, .p_callback = callback_agt,
|
|
/** If NULL then do not add & */
|
|
#if defined(NULL)
|
|
.p_context = NULL,
|
|
#else
|
|
.p_context = &NULL,
|
|
#endif
|
|
.p_extend = &g_timer1_extend,
|
|
.cycle_end_ipl = (5),
|
|
#if defined(VECTOR_NUMBER_AGT0_INT)
|
|
.cycle_end_irq = VECTOR_NUMBER_AGT0_INT,
|
|
#else
|
|
.cycle_end_irq = FSP_INVALID_VECTOR,
|
|
#endif
|
|
};
|
|
/* Instance structure to use this module. */
|
|
const timer_instance_t g_timer1 =
|
|
{ .p_ctrl = &g_timer1_ctrl, .p_cfg = &g_timer1_cfg, .p_api = &g_timer_on_agt };
|
|
agt_instance_ctrl_t g_timer0_ctrl;
|
|
const agt_extended_cfg_t g_timer0_extend =
|
|
{ .count_source = AGT_CLOCK_PCLKB,
|
|
.agto = AGT_PIN_CFG_DISABLED,
|
|
.agtoa = AGT_PIN_CFG_DISABLED,
|
|
.agtob = AGT_PIN_CFG_DISABLED,
|
|
.measurement_mode = AGT_MEASURE_DISABLED,
|
|
.agtio_filter = AGT_AGTIO_FILTER_NONE,
|
|
.enable_pin = AGT_ENABLE_PIN_NOT_USED,
|
|
.trigger_edge = AGT_TRIGGER_EDGE_RISING, };
|
|
const timer_cfg_t g_timer0_cfg =
|
|
{ .mode = TIMER_MODE_PERIODIC,
|
|
/* Actual period: 0.0010922666666666667 seconds. Actual duty: 50%. */ .period_counts = 0x10000,
|
|
.duty_cycle_counts = 0x8000, .source_div = (timer_source_div_t)0, .channel = 0, .p_callback = callback_agt,
|
|
/** If NULL then do not add & */
|
|
#if defined(NULL)
|
|
.p_context = NULL,
|
|
#else
|
|
.p_context = &NULL,
|
|
#endif
|
|
.p_extend = &g_timer0_extend,
|
|
.cycle_end_ipl = (5),
|
|
#if defined(VECTOR_NUMBER_AGT0_INT)
|
|
.cycle_end_irq = VECTOR_NUMBER_AGT0_INT,
|
|
#else
|
|
.cycle_end_irq = FSP_INVALID_VECTOR,
|
|
#endif
|
|
};
|
|
/* Instance structure to use this module. */
|
|
const timer_instance_t g_timer0 =
|
|
{ .p_ctrl = &g_timer0_ctrl, .p_cfg = &g_timer0_cfg, .p_api = &g_timer_on_agt };
|
|
flash_hp_instance_ctrl_t g_flash0_ctrl;
|
|
const flash_cfg_t g_flash0_cfg =
|
|
{ .data_flash_bgo = false, .p_callback = NULL, .p_context = NULL,
|
|
#if defined(VECTOR_NUMBER_FCU_FRDYI)
|
|
.irq = VECTOR_NUMBER_FCU_FRDYI,
|
|
#else
|
|
.irq = FSP_INVALID_VECTOR,
|
|
#endif
|
|
#if defined(VECTOR_NUMBER_FCU_FIFERR)
|
|
.err_irq = VECTOR_NUMBER_FCU_FIFERR,
|
|
#else
|
|
.err_irq = FSP_INVALID_VECTOR,
|
|
#endif
|
|
.err_ipl = (BSP_IRQ_DISABLED),
|
|
.ipl = (BSP_IRQ_DISABLED), };
|
|
/* Instance structure to use this module. */
|
|
const flash_instance_t g_flash0 =
|
|
{ .p_ctrl = &g_flash0_ctrl, .p_cfg = &g_flash0_cfg, .p_api = &g_flash_on_flash_hp };
|
|
rtc_instance_ctrl_t g_rtc0_ctrl;
|
|
const rtc_error_adjustment_cfg_t g_rtc0_err_cfg =
|
|
{ .adjustment_mode = RTC_ERROR_ADJUSTMENT_MODE_AUTOMATIC,
|
|
.adjustment_period = RTC_ERROR_ADJUSTMENT_PERIOD_10_SECOND,
|
|
.adjustment_type = RTC_ERROR_ADJUSTMENT_NONE,
|
|
.adjustment_value = 0, };
|
|
const rtc_cfg_t g_rtc0_cfg =
|
|
{ .clock_source = RTC_CLOCK_SOURCE_LOCO, .freq_compare_value_loco = 255, .p_err_cfg = &g_rtc0_err_cfg, .p_callback =
|
|
NULL,
|
|
.p_context = NULL, .alarm_ipl = (14), .periodic_ipl = (14), .carry_ipl = (14),
|
|
#if defined(VECTOR_NUMBER_RTC_ALARM)
|
|
.alarm_irq = VECTOR_NUMBER_RTC_ALARM,
|
|
#else
|
|
.alarm_irq = FSP_INVALID_VECTOR,
|
|
#endif
|
|
#if defined(VECTOR_NUMBER_RTC_PERIOD)
|
|
.periodic_irq = VECTOR_NUMBER_RTC_PERIOD,
|
|
#else
|
|
.periodic_irq = FSP_INVALID_VECTOR,
|
|
#endif
|
|
#if defined(VECTOR_NUMBER_RTC_CARRY)
|
|
.carry_irq = VECTOR_NUMBER_RTC_CARRY,
|
|
#else
|
|
.carry_irq = FSP_INVALID_VECTOR,
|
|
#endif
|
|
};
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|
/* Instance structure to use this module. */
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|
const rtc_instance_t g_rtc0 =
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|
{ .p_ctrl = &g_rtc0_ctrl, .p_cfg = &g_rtc0_cfg, .p_api = &g_rtc_on_rtc };
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|
sci_uart_instance_ctrl_t g_uart9_ctrl;
|
|
|
|
baud_setting_t g_uart9_baud_setting =
|
|
{
|
|
/* Baud rate calculated with 0.160% error. */ .abcse = 0,
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|
.abcs = 0, .bgdm = 1, .cks = 0, .brr = 64, .mddr = (uint8_t)256, .brme = false
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|
};
|
|
|
|
/** UART extended configuration for UARTonSCI HAL driver */
|
|
const sci_uart_extended_cfg_t g_uart9_cfg_extend =
|
|
{ .clock = SCI_UART_CLOCK_INT,
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|
.rx_edge_start = SCI_UART_START_BIT_FALLING_EDGE,
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|
.noise_cancel = SCI_UART_NOISE_CANCELLATION_DISABLE,
|
|
.rx_fifo_trigger = SCI_UART_RX_FIFO_TRIGGER_MAX,
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|
.p_baud_setting = &g_uart9_baud_setting,
|
|
.uart_mode = UART_MODE_RS232,
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|
.ctsrts_en = SCI_UART_CTSRTS_RTS_OUTPUT,
|
|
#if 0
|
|
.flow_control_pin = BSP_IO_PORT_00_PIN_00,
|
|
#else
|
|
.flow_control_pin = (bsp_io_port_pin_t)(0xFFFFU),
|
|
#endif
|
|
};
|
|
|
|
/** UART interface configuration */
|
|
const uart_cfg_t g_uart9_cfg =
|
|
{ .channel = 9, .data_bits = UART_DATA_BITS_8, .parity = UART_PARITY_OFF, .stop_bits = UART_STOP_BITS_1, .p_callback =
|
|
user_uart_callback,
|
|
.p_context = NULL, .p_extend = &g_uart9_cfg_extend,
|
|
#define RA_NOT_DEFINED (1)
|
|
#if (RA_NOT_DEFINED == RA_NOT_DEFINED)
|
|
.p_transfer_tx = NULL,
|
|
#else
|
|
.p_transfer_tx = &RA_NOT_DEFINED,
|
|
#endif
|
|
#if (RA_NOT_DEFINED == RA_NOT_DEFINED)
|
|
.p_transfer_rx = NULL,
|
|
#else
|
|
.p_transfer_rx = &RA_NOT_DEFINED,
|
|
#endif
|
|
#undef RA_NOT_DEFINED
|
|
.rxi_ipl = (12),
|
|
.txi_ipl = (12), .tei_ipl = (12), .eri_ipl = (12),
|
|
#if defined(VECTOR_NUMBER_SCI9_RXI)
|
|
.rxi_irq = VECTOR_NUMBER_SCI9_RXI,
|
|
#else
|
|
.rxi_irq = FSP_INVALID_VECTOR,
|
|
#endif
|
|
#if defined(VECTOR_NUMBER_SCI9_TXI)
|
|
.txi_irq = VECTOR_NUMBER_SCI9_TXI,
|
|
#else
|
|
.txi_irq = FSP_INVALID_VECTOR,
|
|
#endif
|
|
#if defined(VECTOR_NUMBER_SCI9_TEI)
|
|
.tei_irq = VECTOR_NUMBER_SCI9_TEI,
|
|
#else
|
|
.tei_irq = FSP_INVALID_VECTOR,
|
|
#endif
|
|
#if defined(VECTOR_NUMBER_SCI9_ERI)
|
|
.eri_irq = VECTOR_NUMBER_SCI9_ERI,
|
|
#else
|
|
.eri_irq = FSP_INVALID_VECTOR,
|
|
#endif
|
|
};
|
|
|
|
/* Instance structure to use this module. */
|
|
const uart_instance_t g_uart9 =
|
|
{ .p_ctrl = &g_uart9_ctrl, .p_cfg = &g_uart9_cfg, .p_api = &g_uart_on_sci };
|
|
sci_uart_instance_ctrl_t g_uart7_ctrl;
|
|
|
|
baud_setting_t g_uart7_baud_setting =
|
|
{
|
|
/* Baud rate calculated with 0.160% error. */ .abcse = 0,
|
|
.abcs = 0, .bgdm = 1, .cks = 0, .brr = 64, .mddr = (uint8_t)256, .brme = false
|
|
};
|
|
|
|
/** UART extended configuration for UARTonSCI HAL driver */
|
|
const sci_uart_extended_cfg_t g_uart7_cfg_extend =
|
|
{ .clock = SCI_UART_CLOCK_INT,
|
|
.rx_edge_start = SCI_UART_START_BIT_FALLING_EDGE,
|
|
.noise_cancel = SCI_UART_NOISE_CANCELLATION_DISABLE,
|
|
.rx_fifo_trigger = SCI_UART_RX_FIFO_TRIGGER_MAX,
|
|
.p_baud_setting = &g_uart7_baud_setting,
|
|
.uart_mode = UART_MODE_RS232,
|
|
.ctsrts_en = SCI_UART_CTSRTS_RTS_OUTPUT,
|
|
#if 0
|
|
.flow_control_pin = BSP_IO_PORT_00_PIN_00,
|
|
#else
|
|
.flow_control_pin = (bsp_io_port_pin_t)(0xFFFFU),
|
|
#endif
|
|
};
|
|
|
|
/** UART interface configuration */
|
|
const uart_cfg_t g_uart7_cfg =
|
|
{ .channel = 7, .data_bits = UART_DATA_BITS_8, .parity = UART_PARITY_OFF, .stop_bits = UART_STOP_BITS_1, .p_callback =
|
|
user_uart_callback,
|
|
.p_context = NULL, .p_extend = &g_uart7_cfg_extend,
|
|
#define RA_NOT_DEFINED (1)
|
|
#if (RA_NOT_DEFINED == RA_NOT_DEFINED)
|
|
.p_transfer_tx = NULL,
|
|
#else
|
|
.p_transfer_tx = &RA_NOT_DEFINED,
|
|
#endif
|
|
#if (RA_NOT_DEFINED == RA_NOT_DEFINED)
|
|
.p_transfer_rx = NULL,
|
|
#else
|
|
.p_transfer_rx = &RA_NOT_DEFINED,
|
|
#endif
|
|
#undef RA_NOT_DEFINED
|
|
.rxi_ipl = (12),
|
|
.txi_ipl = (12), .tei_ipl = (12), .eri_ipl = (12),
|
|
#if defined(VECTOR_NUMBER_SCI7_RXI)
|
|
.rxi_irq = VECTOR_NUMBER_SCI7_RXI,
|
|
#else
|
|
.rxi_irq = FSP_INVALID_VECTOR,
|
|
#endif
|
|
#if defined(VECTOR_NUMBER_SCI7_TXI)
|
|
.txi_irq = VECTOR_NUMBER_SCI7_TXI,
|
|
#else
|
|
.txi_irq = FSP_INVALID_VECTOR,
|
|
#endif
|
|
#if defined(VECTOR_NUMBER_SCI7_TEI)
|
|
.tei_irq = VECTOR_NUMBER_SCI7_TEI,
|
|
#else
|
|
.tei_irq = FSP_INVALID_VECTOR,
|
|
#endif
|
|
#if defined(VECTOR_NUMBER_SCI7_ERI)
|
|
.eri_irq = VECTOR_NUMBER_SCI7_ERI,
|
|
#else
|
|
.eri_irq = FSP_INVALID_VECTOR,
|
|
#endif
|
|
};
|
|
|
|
/* Instance structure to use this module. */
|
|
const uart_instance_t g_uart7 =
|
|
{ .p_ctrl = &g_uart7_ctrl, .p_cfg = &g_uart7_cfg, .p_api = &g_uart_on_sci };
|
|
sci_uart_instance_ctrl_t g_uart0_ctrl;
|
|
|
|
baud_setting_t g_uart0_baud_setting =
|
|
{
|
|
/* Baud rate calculated with 0.160% error. */ .abcse = 0,
|
|
.abcs = 0, .bgdm = 1, .cks = 0, .brr = 64, .mddr = (uint8_t)256, .brme = false
|
|
};
|
|
|
|
/** UART extended configuration for UARTonSCI HAL driver */
|
|
const sci_uart_extended_cfg_t g_uart0_cfg_extend =
|
|
{ .clock = SCI_UART_CLOCK_INT,
|
|
.rx_edge_start = SCI_UART_START_BIT_FALLING_EDGE,
|
|
.noise_cancel = SCI_UART_NOISE_CANCELLATION_DISABLE,
|
|
.rx_fifo_trigger = SCI_UART_RX_FIFO_TRIGGER_MAX,
|
|
.p_baud_setting = &g_uart0_baud_setting,
|
|
.uart_mode = UART_MODE_RS232,
|
|
.ctsrts_en = SCI_UART_CTSRTS_RTS_OUTPUT,
|
|
#if 0
|
|
.flow_control_pin = BSP_IO_PORT_00_PIN_00,
|
|
#else
|
|
.flow_control_pin = (bsp_io_port_pin_t)(0xFFFFU),
|
|
#endif
|
|
};
|
|
|
|
/** UART interface configuration */
|
|
const uart_cfg_t g_uart0_cfg =
|
|
{ .channel = 0, .data_bits = UART_DATA_BITS_8, .parity = UART_PARITY_OFF, .stop_bits = UART_STOP_BITS_1, .p_callback =
|
|
user_uart_callback,
|
|
.p_context = NULL, .p_extend = &g_uart0_cfg_extend,
|
|
#define RA_NOT_DEFINED (1)
|
|
#if (RA_NOT_DEFINED == RA_NOT_DEFINED)
|
|
.p_transfer_tx = NULL,
|
|
#else
|
|
.p_transfer_tx = &RA_NOT_DEFINED,
|
|
#endif
|
|
#if (RA_NOT_DEFINED == RA_NOT_DEFINED)
|
|
.p_transfer_rx = NULL,
|
|
#else
|
|
.p_transfer_rx = &RA_NOT_DEFINED,
|
|
#endif
|
|
#undef RA_NOT_DEFINED
|
|
.rxi_ipl = (12),
|
|
.txi_ipl = (12), .tei_ipl = (12), .eri_ipl = (12),
|
|
#if defined(VECTOR_NUMBER_SCI0_RXI)
|
|
.rxi_irq = VECTOR_NUMBER_SCI0_RXI,
|
|
#else
|
|
.rxi_irq = FSP_INVALID_VECTOR,
|
|
#endif
|
|
#if defined(VECTOR_NUMBER_SCI0_TXI)
|
|
.txi_irq = VECTOR_NUMBER_SCI0_TXI,
|
|
#else
|
|
.txi_irq = FSP_INVALID_VECTOR,
|
|
#endif
|
|
#if defined(VECTOR_NUMBER_SCI0_TEI)
|
|
.tei_irq = VECTOR_NUMBER_SCI0_TEI,
|
|
#else
|
|
.tei_irq = FSP_INVALID_VECTOR,
|
|
#endif
|
|
#if defined(VECTOR_NUMBER_SCI0_ERI)
|
|
.eri_irq = VECTOR_NUMBER_SCI0_ERI,
|
|
#else
|
|
.eri_irq = FSP_INVALID_VECTOR,
|
|
#endif
|
|
};
|
|
|
|
/* Instance structure to use this module. */
|
|
const uart_instance_t g_uart0 =
|
|
{ .p_ctrl = &g_uart0_ctrl, .p_cfg = &g_uart0_cfg, .p_api = &g_uart_on_sci };
|
|
void g_hal_init(void) {
|
|
g_common_init();
|
|
}
|