434 lines
11 KiB
C
434 lines
11 KiB
C
/* Auto-generated config file peripheral_clk_config.h */
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#ifndef PERIPHERAL_CLK_CONFIG_H
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#define PERIPHERAL_CLK_CONFIG_H
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// <<< Use Configuration Wizard in Context Menu >>>
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// <y> ADC Clock Source
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// <id> adc_gclk_selection
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// <GCLK_CLKCTRL_GEN_GCLK0_Val"> Generic clock generator 0
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// <GCLK_CLKCTRL_GEN_GCLK1_Val"> Generic clock generator 1
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// <GCLK_CLKCTRL_GEN_GCLK2_Val"> Generic clock generator 2
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// <GCLK_CLKCTRL_GEN_GCLK3_Val"> Generic clock generator 3
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// <GCLK_CLKCTRL_GEN_GCLK4_Val"> Generic clock generator 4
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// <GCLK_CLKCTRL_GEN_GCLK5_Val"> Generic clock generator 5
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// <GCLK_CLKCTRL_GEN_GCLK6_Val"> Generic clock generator 6
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// <GCLK_CLKCTRL_GEN_GCLK7_Val"> Generic clock generator 7
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// <i> Select the clock source for ADC.
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#ifndef CONF_GCLK_ADC_SRC
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#define CONF_GCLK_ADC_SRC GCLK_CLKCTRL_GEN_GCLK0_Val
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#endif
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/**
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* \def CONF_GCLK_ADC_FREQUENCY
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* \brief ADC's Clock frequency
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*/
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#ifndef CONF_GCLK_ADC_FREQUENCY
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#define CONF_GCLK_ADC_FREQUENCY 48000000
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#endif
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/**
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* \def CONF_CPU_FREQUENCY
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* \brief CPU's Clock frequency
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*/
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#ifndef CONF_CPU_FREQUENCY
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#define CONF_CPU_FREQUENCY 48000000
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#endif
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// <y> Core Clock Source
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// <id> core_gclk_selection
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// <GCLK_CLKCTRL_GEN_GCLK0_Val"> Generic clock generator 0
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// <GCLK_CLKCTRL_GEN_GCLK1_Val"> Generic clock generator 1
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// <GCLK_CLKCTRL_GEN_GCLK2_Val"> Generic clock generator 2
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// <GCLK_CLKCTRL_GEN_GCLK3_Val"> Generic clock generator 3
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// <GCLK_CLKCTRL_GEN_GCLK4_Val"> Generic clock generator 4
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// <GCLK_CLKCTRL_GEN_GCLK5_Val"> Generic clock generator 5
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// <GCLK_CLKCTRL_GEN_GCLK6_Val"> Generic clock generator 6
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// <GCLK_CLKCTRL_GEN_GCLK7_Val"> Generic clock generator 7
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// <i> Select the clock source for CORE.
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#ifndef CONF_GCLK_SERCOM0_CORE_SRC
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#define CONF_GCLK_SERCOM0_CORE_SRC GCLK_CLKCTRL_GEN_GCLK0_Val
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#endif
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// <y> Slow Clock Source
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// <id> slow_gclk_selection
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// <GCLK_CLKCTRL_GEN_GCLK0_Val"> Generic clock generator 0
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// <GCLK_CLKCTRL_GEN_GCLK1_Val"> Generic clock generator 1
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// <GCLK_CLKCTRL_GEN_GCLK2_Val"> Generic clock generator 2
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// <GCLK_CLKCTRL_GEN_GCLK3_Val"> Generic clock generator 3
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// <GCLK_CLKCTRL_GEN_GCLK4_Val"> Generic clock generator 4
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// <GCLK_CLKCTRL_GEN_GCLK5_Val"> Generic clock generator 5
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// <GCLK_CLKCTRL_GEN_GCLK6_Val"> Generic clock generator 6
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// <GCLK_CLKCTRL_GEN_GCLK7_Val"> Generic clock generator 7
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// <i> Select the slow clock source.
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#ifndef CONF_GCLK_SERCOM0_SLOW_SRC
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#define CONF_GCLK_SERCOM0_SLOW_SRC GCLK_CLKCTRL_GEN_GCLK3_Val
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#endif
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/**
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* \def CONF_GCLK_SERCOM0_CORE_FREQUENCY
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* \brief SERCOM0's Core Clock frequency
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*/
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#ifndef CONF_GCLK_SERCOM0_CORE_FREQUENCY
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#define CONF_GCLK_SERCOM0_CORE_FREQUENCY 48000000
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#endif
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/**
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* \def CONF_GCLK_SERCOM0_SLOW_FREQUENCY
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* \brief SERCOM0's Slow Clock frequency
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*/
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#ifndef CONF_GCLK_SERCOM0_SLOW_FREQUENCY
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#define CONF_GCLK_SERCOM0_SLOW_FREQUENCY 400000
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#endif
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// <y> Core Clock Source
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// <id> core_gclk_selection
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// <GCLK_CLKCTRL_GEN_GCLK0_Val"> Generic clock generator 0
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// <GCLK_CLKCTRL_GEN_GCLK1_Val"> Generic clock generator 1
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// <GCLK_CLKCTRL_GEN_GCLK2_Val"> Generic clock generator 2
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// <GCLK_CLKCTRL_GEN_GCLK3_Val"> Generic clock generator 3
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// <GCLK_CLKCTRL_GEN_GCLK4_Val"> Generic clock generator 4
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// <GCLK_CLKCTRL_GEN_GCLK5_Val"> Generic clock generator 5
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// <GCLK_CLKCTRL_GEN_GCLK6_Val"> Generic clock generator 6
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// <GCLK_CLKCTRL_GEN_GCLK7_Val"> Generic clock generator 7
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// <i> Select the clock source for CORE.
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#ifndef CONF_GCLK_SERCOM1_CORE_SRC
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#define CONF_GCLK_SERCOM1_CORE_SRC GCLK_CLKCTRL_GEN_GCLK0_Val
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#endif
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// <y> Slow Clock Source
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// <id> slow_gclk_selection
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// <GCLK_CLKCTRL_GEN_GCLK0_Val"> Generic clock generator 0
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// <GCLK_CLKCTRL_GEN_GCLK1_Val"> Generic clock generator 1
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// <GCLK_CLKCTRL_GEN_GCLK2_Val"> Generic clock generator 2
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// <GCLK_CLKCTRL_GEN_GCLK3_Val"> Generic clock generator 3
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// <GCLK_CLKCTRL_GEN_GCLK4_Val"> Generic clock generator 4
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// <GCLK_CLKCTRL_GEN_GCLK5_Val"> Generic clock generator 5
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// <GCLK_CLKCTRL_GEN_GCLK6_Val"> Generic clock generator 6
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// <GCLK_CLKCTRL_GEN_GCLK7_Val"> Generic clock generator 7
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// <i> Select the slow clock source.
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#ifndef CONF_GCLK_SERCOM1_SLOW_SRC
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#define CONF_GCLK_SERCOM1_SLOW_SRC GCLK_CLKCTRL_GEN_GCLK3_Val
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#endif
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/**
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* \def CONF_GCLK_SERCOM1_CORE_FREQUENCY
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* \brief SERCOM1's Core Clock frequency
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*/
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#ifndef CONF_GCLK_SERCOM1_CORE_FREQUENCY
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#define CONF_GCLK_SERCOM1_CORE_FREQUENCY 48000000
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#endif
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/**
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* \def CONF_GCLK_SERCOM1_SLOW_FREQUENCY
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* \brief SERCOM1's Slow Clock frequency
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*/
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#ifndef CONF_GCLK_SERCOM1_SLOW_FREQUENCY
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#define CONF_GCLK_SERCOM1_SLOW_FREQUENCY 400000
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#endif
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// <y> Core Clock Source
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// <id> core_gclk_selection
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// <GCLK_CLKCTRL_GEN_GCLK0_Val"> Generic clock generator 0
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// <GCLK_CLKCTRL_GEN_GCLK1_Val"> Generic clock generator 1
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// <GCLK_CLKCTRL_GEN_GCLK2_Val"> Generic clock generator 2
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// <GCLK_CLKCTRL_GEN_GCLK3_Val"> Generic clock generator 3
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// <GCLK_CLKCTRL_GEN_GCLK4_Val"> Generic clock generator 4
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// <GCLK_CLKCTRL_GEN_GCLK5_Val"> Generic clock generator 5
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// <GCLK_CLKCTRL_GEN_GCLK6_Val"> Generic clock generator 6
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// <GCLK_CLKCTRL_GEN_GCLK7_Val"> Generic clock generator 7
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// <i> Select the clock source for CORE.
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#ifndef CONF_GCLK_SERCOM2_CORE_SRC
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#define CONF_GCLK_SERCOM2_CORE_SRC GCLK_CLKCTRL_GEN_GCLK0_Val
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#endif
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// <y> Slow Clock Source
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// <id> slow_gclk_selection
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// <GCLK_CLKCTRL_GEN_GCLK0_Val"> Generic clock generator 0
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// <GCLK_CLKCTRL_GEN_GCLK1_Val"> Generic clock generator 1
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// <GCLK_CLKCTRL_GEN_GCLK2_Val"> Generic clock generator 2
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// <GCLK_CLKCTRL_GEN_GCLK3_Val"> Generic clock generator 3
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// <GCLK_CLKCTRL_GEN_GCLK4_Val"> Generic clock generator 4
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// <GCLK_CLKCTRL_GEN_GCLK5_Val"> Generic clock generator 5
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// <GCLK_CLKCTRL_GEN_GCLK6_Val"> Generic clock generator 6
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// <GCLK_CLKCTRL_GEN_GCLK7_Val"> Generic clock generator 7
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// <i> Select the slow clock source.
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#ifndef CONF_GCLK_SERCOM2_SLOW_SRC
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#define CONF_GCLK_SERCOM2_SLOW_SRC GCLK_CLKCTRL_GEN_GCLK3_Val
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#endif
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/**
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* \def CONF_GCLK_SERCOM2_CORE_FREQUENCY
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* \brief SERCOM2's Core Clock frequency
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*/
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#ifndef CONF_GCLK_SERCOM2_CORE_FREQUENCY
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#define CONF_GCLK_SERCOM2_CORE_FREQUENCY 48000000
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#endif
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/**
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* \def CONF_GCLK_SERCOM2_SLOW_FREQUENCY
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* \brief SERCOM2's Slow Clock frequency
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*/
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#ifndef CONF_GCLK_SERCOM2_SLOW_FREQUENCY
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#define CONF_GCLK_SERCOM2_SLOW_FREQUENCY 400000
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#endif
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// <y> Core Clock Source
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// <id> core_gclk_selection
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// <GCLK_CLKCTRL_GEN_GCLK0_Val"> Generic clock generator 0
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// <GCLK_CLKCTRL_GEN_GCLK1_Val"> Generic clock generator 1
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// <GCLK_CLKCTRL_GEN_GCLK2_Val"> Generic clock generator 2
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// <GCLK_CLKCTRL_GEN_GCLK3_Val"> Generic clock generator 3
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// <GCLK_CLKCTRL_GEN_GCLK4_Val"> Generic clock generator 4
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// <GCLK_CLKCTRL_GEN_GCLK5_Val"> Generic clock generator 5
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// <GCLK_CLKCTRL_GEN_GCLK6_Val"> Generic clock generator 6
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// <GCLK_CLKCTRL_GEN_GCLK7_Val"> Generic clock generator 7
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// <i> Select the clock source for CORE.
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#ifndef CONF_GCLK_SERCOM3_CORE_SRC
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#define CONF_GCLK_SERCOM3_CORE_SRC GCLK_CLKCTRL_GEN_GCLK0_Val
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#endif
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// <y> Slow Clock Source
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// <id> slow_gclk_selection
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// <GCLK_CLKCTRL_GEN_GCLK0_Val"> Generic clock generator 0
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// <GCLK_CLKCTRL_GEN_GCLK1_Val"> Generic clock generator 1
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// <GCLK_CLKCTRL_GEN_GCLK2_Val"> Generic clock generator 2
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// <GCLK_CLKCTRL_GEN_GCLK3_Val"> Generic clock generator 3
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// <GCLK_CLKCTRL_GEN_GCLK4_Val"> Generic clock generator 4
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// <GCLK_CLKCTRL_GEN_GCLK5_Val"> Generic clock generator 5
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// <GCLK_CLKCTRL_GEN_GCLK6_Val"> Generic clock generator 6
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// <GCLK_CLKCTRL_GEN_GCLK7_Val"> Generic clock generator 7
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// <i> Select the slow clock source.
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#ifndef CONF_GCLK_SERCOM3_SLOW_SRC
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#define CONF_GCLK_SERCOM3_SLOW_SRC GCLK_CLKCTRL_GEN_GCLK3_Val
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#endif
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/**
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* \def CONF_GCLK_SERCOM3_CORE_FREQUENCY
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* \brief SERCOM3's Core Clock frequency
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*/
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#ifndef CONF_GCLK_SERCOM3_CORE_FREQUENCY
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#define CONF_GCLK_SERCOM3_CORE_FREQUENCY 48000000
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#endif
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/**
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* \def CONF_GCLK_SERCOM3_SLOW_FREQUENCY
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* \brief SERCOM3's Slow Clock frequency
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*/
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#ifndef CONF_GCLK_SERCOM3_SLOW_FREQUENCY
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#define CONF_GCLK_SERCOM3_SLOW_FREQUENCY 400000
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#endif
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// <y> RTC Clock Source
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// <id> rtc_clk_selection
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// <GCLK_CLKCTRL_GEN_GCLK0_Val"> Generic clock generator 0
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// <GCLK_CLKCTRL_GEN_GCLK1_Val"> Generic clock generator 1
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// <GCLK_CLKCTRL_GEN_GCLK2_Val"> Generic clock generator 2
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// <GCLK_CLKCTRL_GEN_GCLK3_Val"> Generic clock generator 3
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// <GCLK_CLKCTRL_GEN_GCLK4_Val"> Generic clock generator 4
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// <GCLK_CLKCTRL_GEN_GCLK5_Val"> Generic clock generator 5
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// <GCLK_CLKCTRL_GEN_GCLK6_Val"> Generic clock generator 6
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// <GCLK_CLKCTRL_GEN_GCLK7_Val"> Generic clock generator 7
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// <i> Select the clock source for RTC.
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#ifndef CONF_GCLK_RTC_SRC
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#define CONF_GCLK_RTC_SRC GCLK_CLKCTRL_GEN_GCLK2_Val
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#endif
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/**
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* \def CONF_GCLK_RTC_FREQUENCY
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* \brief RTC's Clock frequency
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*/
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#ifndef CONF_GCLK_RTC_FREQUENCY
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#define CONF_GCLK_RTC_FREQUENCY 48000000
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#endif
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// <y> TC Clock Source
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// <id> tc_gclk_selection
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// <GCLK_CLKCTRL_GEN_GCLK0_Val"> Generic clock generator 0
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// <GCLK_CLKCTRL_GEN_GCLK1_Val"> Generic clock generator 1
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// <GCLK_CLKCTRL_GEN_GCLK2_Val"> Generic clock generator 2
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// <GCLK_CLKCTRL_GEN_GCLK3_Val"> Generic clock generator 3
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// <GCLK_CLKCTRL_GEN_GCLK4_Val"> Generic clock generator 4
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// <GCLK_CLKCTRL_GEN_GCLK5_Val"> Generic clock generator 5
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// <GCLK_CLKCTRL_GEN_GCLK6_Val"> Generic clock generator 6
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// <GCLK_CLKCTRL_GEN_GCLK7_Val"> Generic clock generator 7
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// <i> Select the clock source for TC.
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#ifndef CONF_GCLK_TC3_SRC
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#define CONF_GCLK_TC3_SRC GCLK_CLKCTRL_GEN_GCLK0_Val
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#endif
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/**
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* \def CONF_GCLK_TC3_FREQUENCY
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* \brief TC3's Clock frequency
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*/
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#ifndef CONF_GCLK_TC3_FREQUENCY
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#define CONF_GCLK_TC3_FREQUENCY 48000000
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#endif
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// <y> DAC Clock Source
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// <id> dac_gclk_selection
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// <GCLK_CLKCTRL_GEN_GCLK0_Val"> Generic clock generator 0
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// <GCLK_CLKCTRL_GEN_GCLK1_Val"> Generic clock generator 1
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// <GCLK_CLKCTRL_GEN_GCLK2_Val"> Generic clock generator 2
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// <GCLK_CLKCTRL_GEN_GCLK3_Val"> Generic clock generator 3
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// <GCLK_CLKCTRL_GEN_GCLK4_Val"> Generic clock generator 4
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// <GCLK_CLKCTRL_GEN_GCLK5_Val"> Generic clock generator 5
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// <GCLK_CLKCTRL_GEN_GCLK6_Val"> Generic clock generator 6
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// <GCLK_CLKCTRL_GEN_GCLK7_Val"> Generic clock generator 7
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// <i> Select the clock source for DAC.
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#ifndef CONF_GCLK_DAC_SRC
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#define CONF_GCLK_DAC_SRC GCLK_CLKCTRL_GEN_GCLK0_Val
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#endif
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/**
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* \def CONF_GCLK_DAC_FREQUENCY
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* \brief DAC's Clock frequency
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*/
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#ifndef CONF_GCLK_DAC_FREQUENCY
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#define CONF_GCLK_DAC_FREQUENCY 48000000
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#endif
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// <y> USB Clock Source
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// <id> usb_gclk_selection
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// <GCLK_CLKCTRL_GEN_GCLK0_Val"> Generic clock generator 0
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// <GCLK_CLKCTRL_GEN_GCLK1_Val"> Generic clock generator 1
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// <GCLK_CLKCTRL_GEN_GCLK2_Val"> Generic clock generator 2
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// <GCLK_CLKCTRL_GEN_GCLK3_Val"> Generic clock generator 3
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// <GCLK_CLKCTRL_GEN_GCLK4_Val"> Generic clock generator 4
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// <GCLK_CLKCTRL_GEN_GCLK5_Val"> Generic clock generator 5
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// <GCLK_CLKCTRL_GEN_GCLK6_Val"> Generic clock generator 6
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// <GCLK_CLKCTRL_GEN_GCLK7_Val"> Generic clock generator 7
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// <i> Select the clock source for USB.
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#ifndef CONF_GCLK_USB_SRC
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#define CONF_GCLK_USB_SRC GCLK_CLKCTRL_GEN_GCLK0_Val
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#endif
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/**
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* \def CONF_GCLK_USB_FREQUENCY
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* \brief USB's Clock frequency
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*/
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#ifndef CONF_GCLK_USB_FREQUENCY
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#define CONF_GCLK_USB_FREQUENCY 48000000
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#endif
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// <<< end of configuration section >>>
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#endif // PERIPHERAL_CLK_CONFIG_H
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