3ef911345c
This patch updates ST's HAL to the latest version, V1.3.0, dated 19 June 2014. Files were copied verbatim from the ST package. Only change was to suppress compiler warning of unused variables in 4 places. A lot of the changes from ST are cosmetic: comments and white space. Some small code changes here and there, and addition of F411 header. Main code change is how SysTick interrupt is set: it now has a configuration variable to set the priority, so we no longer need to work around this (originall in system_stm32f4xx.c).
782 lines
37 KiB
C
782 lines
37 KiB
C
/**
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******************************************************************************
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* @file stm32f4xx_hal_can.h
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* @author MCD Application Team
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* @version V1.1.0
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* @date 19-June-2014
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* @brief Header file of CAN HAL module.
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of STMicroelectronics nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __STM32F4xx_HAL_CAN_H
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#define __STM32F4xx_HAL_CAN_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
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/* Includes ------------------------------------------------------------------*/
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#include "stm32f4xx_hal_def.h"
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/** @addtogroup STM32F4xx_HAL_Driver
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* @{
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*/
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/** @addtogroup CAN
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* @{
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*/
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/* Exported types ------------------------------------------------------------*/
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/**
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* @brief HAL State structures definition
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*/
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typedef enum
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{
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HAL_CAN_STATE_RESET = 0x00, /*!< CAN not yet initialized or disabled */
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HAL_CAN_STATE_READY = 0x01, /*!< CAN initialized and ready for use */
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HAL_CAN_STATE_BUSY = 0x02, /*!< CAN process is ongoing */
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HAL_CAN_STATE_BUSY_TX = 0x12, /*!< CAN process is ongoing */
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HAL_CAN_STATE_BUSY_RX = 0x22, /*!< CAN process is ongoing */
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HAL_CAN_STATE_BUSY_TX_RX = 0x32, /*!< CAN process is ongoing */
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HAL_CAN_STATE_TIMEOUT = 0x03, /*!< Timeout state */
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HAL_CAN_STATE_ERROR = 0x04 /*!< CAN error state */
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}HAL_CAN_StateTypeDef;
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/**
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* @brief CAN init structure definition
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*/
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typedef struct
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{
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uint32_t Prescaler; /*!< Specifies the length of a time quantum.
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This parameter must be a number between Min_Data = 1 and Max_Data = 1024 */
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uint32_t Mode; /*!< Specifies the CAN operating mode.
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This parameter can be a value of @ref CAN_operating_mode */
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uint32_t SJW; /*!< Specifies the maximum number of time quanta
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the CAN hardware is allowed to lengthen or
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shorten a bit to perform resynchronization.
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This parameter can be a value of @ref CAN_synchronisation_jump_width */
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uint32_t BS1; /*!< Specifies the number of time quanta in Bit Segment 1.
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This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */
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uint32_t BS2; /*!< Specifies the number of time quanta in Bit Segment 2.
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This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */
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uint32_t TTCM; /*!< Enable or disable the time triggered communication mode.
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This parameter can be set to ENABLE or DISABLE. */
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uint32_t ABOM; /*!< Enable or disable the automatic bus-off management.
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This parameter can be set to ENABLE or DISABLE */
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uint32_t AWUM; /*!< Enable or disable the automatic wake-up mode.
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This parameter can be set to ENABLE or DISABLE */
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uint32_t NART; /*!< Enable or disable the non-automatic retransmission mode.
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This parameter can be set to ENABLE or DISABLE */
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uint32_t RFLM; /*!< Enable or disable the receive FIFO Locked mode.
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This parameter can be set to ENABLE or DISABLE */
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uint32_t TXFP; /*!< Enable or disable the transmit FIFO priority.
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This parameter can be set to ENABLE or DISABLE */
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}CAN_InitTypeDef;
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/**
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* @brief CAN filter configuration structure definition
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*/
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typedef struct
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{
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uint32_t FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit
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configuration, first one for a 16-bit configuration).
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This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
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uint32_t FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit
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configuration, second one for a 16-bit configuration).
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This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
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uint32_t FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number,
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according to the mode (MSBs for a 32-bit configuration,
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first one for a 16-bit configuration).
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This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
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uint32_t FilterMaskIdLow; /*!< Specifies the filter mask number or identification number,
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according to the mode (LSBs for a 32-bit configuration,
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second one for a 16-bit configuration).
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This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
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uint32_t FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter.
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This parameter can be a value of @ref CAN_filter_FIFO */
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uint32_t FilterNumber; /*!< Specifies the filter which will be initialized.
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This parameter must be a number between Min_Data = 0 and Max_Data = 27 */
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uint32_t FilterMode; /*!< Specifies the filter mode to be initialized.
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This parameter can be a value of @ref CAN_filter_mode */
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uint32_t FilterScale; /*!< Specifies the filter scale.
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This parameter can be a value of @ref CAN_filter_scale */
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uint32_t FilterActivation; /*!< Enable or disable the filter.
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This parameter can be set to ENABLE or DISABLE. */
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uint32_t BankNumber; /*!< Select the start slave bank filter.
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This parameter must be a number between Min_Data = 0 and Max_Data = 28 */
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}CAN_FilterConfTypeDef;
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/**
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* @brief CAN Tx message structure definition
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*/
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typedef struct
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{
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uint32_t StdId; /*!< Specifies the standard identifier.
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This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */
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uint32_t ExtId; /*!< Specifies the extended identifier.
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This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */
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uint32_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted.
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This parameter can be a value of @ref CAN_identifier_type */
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uint32_t RTR; /*!< Specifies the type of frame for the message that will be transmitted.
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This parameter can be a value of @ref CAN_remote_transmission_request */
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uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted.
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This parameter must be a number between Min_Data = 0 and Max_Data = 8 */
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uint32_t Data[8]; /*!< Contains the data to be transmitted.
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This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */
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}CanTxMsgTypeDef;
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/**
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* @brief CAN Rx message structure definition
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*/
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typedef struct
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{
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uint32_t StdId; /*!< Specifies the standard identifier.
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This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */
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uint32_t ExtId; /*!< Specifies the extended identifier.
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This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */
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uint32_t IDE; /*!< Specifies the type of identifier for the message that will be received.
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This parameter can be a value of @ref CAN_identifier_type */
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uint32_t RTR; /*!< Specifies the type of frame for the received message.
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This parameter can be a value of @ref CAN_remote_transmission_request */
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uint32_t DLC; /*!< Specifies the length of the frame that will be received.
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This parameter must be a number between Min_Data = 0 and Max_Data = 8 */
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uint32_t Data[8]; /*!< Contains the data to be received.
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This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */
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uint32_t FMI; /*!< Specifies the index of the filter the message stored in the mailbox passes through.
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This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */
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uint32_t FIFONumber; /*!< Specifies the receive FIFO number.
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This parameter can be CAN_FIFO0 or CAN_FIFO1 */
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}CanRxMsgTypeDef;
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/**
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* @brief CAN handle Structure definition
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*/
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typedef struct
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{
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CAN_TypeDef *Instance; /*!< Register base address */
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CAN_InitTypeDef Init; /*!< CAN required parameters */
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CanTxMsgTypeDef* pTxMsg; /*!< Pointer to transmit structure */
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CanRxMsgTypeDef* pRxMsg; /*!< Pointer to reception structure */
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__IO HAL_CAN_StateTypeDef State; /*!< CAN communication state */
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HAL_LockTypeDef Lock; /*!< CAN locking object */
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__IO uint32_t ErrorCode; /*!< CAN Error code */
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}CAN_HandleTypeDef;
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/* Exported constants --------------------------------------------------------*/
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/** @defgroup CAN_Exported_Constants
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* @{
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*/
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/** @defgroup HAL CAN Error Code
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* @{
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*/
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#define HAL_CAN_ERROR_NONE 0x00 /*!< No error */
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#define HAL_CAN_ERROR_EWG 0x01 /*!< EWG error */
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#define HAL_CAN_ERROR_EPV 0x02 /*!< EPV error */
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#define HAL_CAN_ERROR_BOF 0x04 /*!< BOF error */
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#define HAL_CAN_ERROR_STF 0x08 /*!< Stuff error */
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#define HAL_CAN_ERROR_FOR 0x10 /*!< Form error */
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#define HAL_CAN_ERROR_ACK 0x20 /*!< Acknowledgment error */
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#define HAL_CAN_ERROR_BR 0x40 /*!< Bit recessive */
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#define HAL_CAN_ERROR_BD 0x80 /*!< LEC dominant */
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#define HAL_CAN_ERROR_CRC 0x100 /*!< LEC transfer error */
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/**
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* @}
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*/
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/** @defgroup CAN_InitStatus
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* @{
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*/
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#define CAN_INITSTATUS_FAILED ((uint8_t)0x00) /*!< CAN initialization failed */
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#define CAN_INITSTATUS_SUCCESS ((uint8_t)0x01) /*!< CAN initialization OK */
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/**
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* @}
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*/
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/** @defgroup CAN_operating_mode
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* @{
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*/
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#define CAN_MODE_NORMAL ((uint32_t)0x00000000) /*!< Normal mode */
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#define CAN_MODE_LOOPBACK ((uint32_t)CAN_BTR_LBKM) /*!< Loopback mode */
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#define CAN_MODE_SILENT ((uint32_t)CAN_BTR_SILM) /*!< Silent mode */
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#define CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM)) /*!< Loopback combined with silent mode */
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#define IS_CAN_MODE(MODE) (((MODE) == CAN_MODE_NORMAL) || \
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((MODE) == CAN_MODE_LOOPBACK)|| \
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((MODE) == CAN_MODE_SILENT) || \
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((MODE) == CAN_MODE_SILENT_LOOPBACK))
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/**
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* @}
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*/
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/** @defgroup CAN_synchronisation_jump_width
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* @{
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*/
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#define CAN_SJW_1TQ ((uint32_t)0x00000000) /*!< 1 time quantum */
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#define CAN_SJW_2TQ ((uint32_t)CAN_BTR_SJW_0) /*!< 2 time quantum */
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#define CAN_SJW_3TQ ((uint32_t)CAN_BTR_SJW_1) /*!< 3 time quantum */
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#define CAN_SJW_4TQ ((uint32_t)CAN_BTR_SJW) /*!< 4 time quantum */
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#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ)|| \
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((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ))
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/**
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* @}
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*/
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/** @defgroup CAN_time_quantum_in_bit_segment_1
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* @{
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*/
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#define CAN_BS1_1TQ ((uint32_t)0x00000000) /*!< 1 time quantum */
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#define CAN_BS1_2TQ ((uint32_t)CAN_BTR_TS1_0) /*!< 2 time quantum */
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#define CAN_BS1_3TQ ((uint32_t)CAN_BTR_TS1_1) /*!< 3 time quantum */
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#define CAN_BS1_4TQ ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 4 time quantum */
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#define CAN_BS1_5TQ ((uint32_t)CAN_BTR_TS1_2) /*!< 5 time quantum */
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#define CAN_BS1_6TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 6 time quantum */
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#define CAN_BS1_7TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 7 time quantum */
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#define CAN_BS1_8TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 8 time quantum */
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#define CAN_BS1_9TQ ((uint32_t)CAN_BTR_TS1_3) /*!< 9 time quantum */
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#define CAN_BS1_10TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_0)) /*!< 10 time quantum */
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#define CAN_BS1_11TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1)) /*!< 11 time quantum */
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#define CAN_BS1_12TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 12 time quantum */
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#define CAN_BS1_13TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2)) /*!< 13 time quantum */
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#define CAN_BS1_14TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 14 time quantum */
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#define CAN_BS1_15TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 15 time quantum */
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#define CAN_BS1_16TQ ((uint32_t)CAN_BTR_TS1) /*!< 16 time quantum */
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#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16TQ)
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/**
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* @}
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*/
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/** @defgroup CAN_time_quantum_in_bit_segment_2
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* @{
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*/
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#define CAN_BS2_1TQ ((uint32_t)0x00000000) /*!< 1 time quantum */
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#define CAN_BS2_2TQ ((uint32_t)CAN_BTR_TS2_0) /*!< 2 time quantum */
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#define CAN_BS2_3TQ ((uint32_t)CAN_BTR_TS2_1) /*!< 3 time quantum */
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#define CAN_BS2_4TQ ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0)) /*!< 4 time quantum */
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#define CAN_BS2_5TQ ((uint32_t)CAN_BTR_TS2_2) /*!< 5 time quantum */
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#define CAN_BS2_6TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_0)) /*!< 6 time quantum */
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#define CAN_BS2_7TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_1)) /*!< 7 time quantum */
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#define CAN_BS2_8TQ ((uint32_t)CAN_BTR_TS2) /*!< 8 time quantum */
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#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8TQ)
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/**
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* @}
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*/
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/** @defgroup CAN_clock_prescaler
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* @{
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*/
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#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024))
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/**
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* @}
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*/
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/** @defgroup CAN_filter_number
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* @{
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*/
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#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27)
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/**
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* @}
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*/
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/** @defgroup CAN_filter_mode
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* @{
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*/
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#define CAN_FILTERMODE_IDMASK ((uint8_t)0x00) /*!< Identifier mask mode */
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#define CAN_FILTERMODE_IDLIST ((uint8_t)0x01) /*!< Identifier list mode */
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#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \
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((MODE) == CAN_FILTERMODE_IDLIST))
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/**
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* @}
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*/
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/** @defgroup CAN_filter_scale
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* @{
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*/
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#define CAN_FILTERSCALE_16BIT ((uint8_t)0x00) /*!< Two 16-bit filters */
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#define CAN_FILTERSCALE_32BIT ((uint8_t)0x01) /*!< One 32-bit filter */
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#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \
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((SCALE) == CAN_FILTERSCALE_32BIT))
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/**
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* @}
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*/
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/** @defgroup CAN_filter_FIFO
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* @{
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*/
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#define CAN_FILTER_FIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */
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#define CAN_FILTER_FIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */
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#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \
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((FIFO) == CAN_FILTER_FIFO1))
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/* Legacy defines */
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#define CAN_FilterFIFO0 CAN_FILTER_FIFO0
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#define CAN_FilterFIFO1 CAN_FILTER_FIFO1
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/**
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* @}
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*/
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/** @defgroup CAN_Start_bank_filter_for_slave_CAN
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* @{
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*/
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#define IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28)
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/**
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* @}
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*/
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/** @defgroup CAN_Tx
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* @{
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*/
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#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))
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#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF))
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#define IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF))
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#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08))
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/**
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* @}
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*/
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/** @defgroup CAN_identifier_type
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* @{
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*/
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#define CAN_ID_STD ((uint32_t)0x00000000) /*!< Standard Id */
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#define CAN_ID_EXT ((uint32_t)0x00000004) /*!< Extended Id */
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#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || \
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((IDTYPE) == CAN_ID_EXT))
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/**
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* @}
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*/
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/** @defgroup CAN_remote_transmission_request
|
|
* @{
|
|
*/
|
|
#define CAN_RTR_DATA ((uint32_t)0x00000000) /*!< Data frame */
|
|
#define CAN_RTR_REMOTE ((uint32_t)0x00000002) /*!< Remote frame */
|
|
#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE))
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup CAN_transmit_constants
|
|
* @{
|
|
*/
|
|
#define CAN_TXSTATUS_FAILED ((uint8_t)0x00) /*!< CAN transmission failed */
|
|
#define CAN_TXSTATUS_OK ((uint8_t)0x01) /*!< CAN transmission succeeded */
|
|
#define CAN_TXSTATUS_PENDING ((uint8_t)0x02) /*!< CAN transmission pending */
|
|
#define CAN_TXSTATUS_NOMAILBOX ((uint8_t)0x04) /*!< CAN cell did not provide CAN_TxStatus_NoMailBox */
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup CAN_receive_FIFO_number_constants
|
|
* @{
|
|
*/
|
|
#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */
|
|
#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */
|
|
|
|
#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup CAN_flags
|
|
* @{
|
|
*/
|
|
/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus()
|
|
and CAN_ClearFlag() functions. */
|
|
/* If the flag is 0x1XXXXXXX, it means that it can only be used with
|
|
CAN_GetFlagStatus() function. */
|
|
|
|
/* Transmit Flags */
|
|
#define CAN_FLAG_RQCP0 ((uint32_t)0x00000500) /*!< Request MailBox0 flag */
|
|
#define CAN_FLAG_RQCP1 ((uint32_t)0x00000508) /*!< Request MailBox1 flag */
|
|
#define CAN_FLAG_RQCP2 ((uint32_t)0x00000510) /*!< Request MailBox2 flag */
|
|
#define CAN_FLAG_TXOK0 ((uint32_t)0x00000501) /*!< Transmission OK MailBox0 flag */
|
|
#define CAN_FLAG_TXOK1 ((uint32_t)0x00000509) /*!< Transmission OK MailBox1 flag */
|
|
#define CAN_FLAG_TXOK2 ((uint32_t)0x00000511) /*!< Transmission OK MailBox2 flag */
|
|
#define CAN_FLAG_TME0 ((uint32_t)0x0000051A) /*!< Transmit mailbox 0 empty flag */
|
|
#define CAN_FLAG_TME1 ((uint32_t)0x0000051B) /*!< Transmit mailbox 0 empty flag */
|
|
#define CAN_FLAG_TME2 ((uint32_t)0x0000051C) /*!< Transmit mailbox 0 empty flag */
|
|
|
|
/* Receive Flags */
|
|
#define CAN_FLAG_FF0 ((uint32_t)0x00000203) /*!< FIFO 0 Full flag */
|
|
#define CAN_FLAG_FOV0 ((uint32_t)0x00000204) /*!< FIFO 0 Overrun flag */
|
|
|
|
#define CAN_FLAG_FF1 ((uint32_t)0x00000403) /*!< FIFO 1 Full flag */
|
|
#define CAN_FLAG_FOV1 ((uint32_t)0x00000404) /*!< FIFO 1 Overrun flag */
|
|
|
|
/* Operating Mode Flags */
|
|
#define CAN_FLAG_WKU ((uint32_t)0x00000103) /*!< Wake up flag */
|
|
#define CAN_FLAG_SLAK ((uint32_t)0x00000101) /*!< Sleep acknowledge flag */
|
|
#define CAN_FLAG_SLAKI ((uint32_t)0x00000104) /*!< Sleep acknowledge flag */
|
|
/* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible.
|
|
In this case the SLAK bit can be polled.*/
|
|
|
|
/* Error Flags */
|
|
#define CAN_FLAG_EWG ((uint32_t)0x00000300) /*!< Error warning flag */
|
|
#define CAN_FLAG_EPV ((uint32_t)0x00000301) /*!< Error passive flag */
|
|
#define CAN_FLAG_BOF ((uint32_t)0x00000302) /*!< Bus-Off flag */
|
|
|
|
#define IS_CAN_GET_FLAG(FLAG) (((FLAG) == CAN_FLAG_RQCP2) || ((FLAG) == CAN_FLAG_BOF) || \
|
|
((FLAG) == CAN_FLAG_EPV) || ((FLAG) == CAN_FLAG_EWG) || \
|
|
((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_FOV0) || \
|
|
((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_SLAK) || \
|
|
((FLAG) == CAN_FLAG_FOV1) || ((FLAG) == CAN_FLAG_FF1) || \
|
|
((FLAG) == CAN_FLAG_RQCP1) || ((FLAG) == CAN_FLAG_RQCP0))
|
|
|
|
|
|
#define IS_CAN_CLEAR_FLAG(FLAG)(((FLAG) == CAN_FLAG_SLAK) || ((FLAG) == CAN_FLAG_RQCP2) || \
|
|
((FLAG) == CAN_FLAG_RQCP1) || ((FLAG) == CAN_FLAG_RQCP0) || \
|
|
((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FOV0) || \
|
|
((FLAG) == CAN_FLAG_FF1) || ((FLAG) == CAN_FLAG_FOV1) || \
|
|
((FLAG) == CAN_FLAG_WKU))
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
|
|
/** @defgroup CAN_interrupts
|
|
* @{
|
|
*/
|
|
#define CAN_IT_TME ((uint32_t)CAN_IER_TMEIE) /*!< Transmit mailbox empty interrupt */
|
|
|
|
/* Receive Interrupts */
|
|
#define CAN_IT_FMP0 ((uint32_t)CAN_IER_FMPIE0) /*!< FIFO 0 message pending interrupt */
|
|
#define CAN_IT_FF0 ((uint32_t)CAN_IER_FFIE0) /*!< FIFO 0 full interrupt */
|
|
#define CAN_IT_FOV0 ((uint32_t)CAN_IER_FOVIE0) /*!< FIFO 0 overrun interrupt */
|
|
#define CAN_IT_FMP1 ((uint32_t)CAN_IER_FMPIE1) /*!< FIFO 1 message pending interrupt */
|
|
#define CAN_IT_FF1 ((uint32_t)CAN_IER_FFIE1) /*!< FIFO 1 full interrupt */
|
|
#define CAN_IT_FOV1 ((uint32_t)CAN_IER_FOVIE1) /*!< FIFO 1 overrun interrupt */
|
|
|
|
/* Operating Mode Interrupts */
|
|
#define CAN_IT_WKU ((uint32_t)CAN_IER_WKUIE) /*!< Wake-up interrupt */
|
|
#define CAN_IT_SLK ((uint32_t)CAN_IER_SLKIE) /*!< Sleep acknowledge interrupt */
|
|
|
|
/* Error Interrupts */
|
|
#define CAN_IT_EWG ((uint32_t)CAN_IER_EWGIE) /*!< Error warning interrupt */
|
|
#define CAN_IT_EPV ((uint32_t)CAN_IER_EPVIE) /*!< Error passive interrupt */
|
|
#define CAN_IT_BOF ((uint32_t)CAN_IER_BOFIE) /*!< Bus-off interrupt */
|
|
#define CAN_IT_LEC ((uint32_t)CAN_IER_LECIE) /*!< Last error code interrupt */
|
|
#define CAN_IT_ERR ((uint32_t)CAN_IER_ERRIE) /*!< Error Interrupt */
|
|
|
|
/* Flags named as Interrupts : kept only for FW compatibility */
|
|
#define CAN_IT_RQCP0 CAN_IT_TME
|
|
#define CAN_IT_RQCP1 CAN_IT_TME
|
|
#define CAN_IT_RQCP2 CAN_IT_TME
|
|
|
|
#define IS_CAN_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0) ||\
|
|
((IT) == CAN_IT_FF0) || ((IT) == CAN_IT_FOV0) ||\
|
|
((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1) ||\
|
|
((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\
|
|
((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\
|
|
((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\
|
|
((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))
|
|
|
|
#define IS_CAN_CLEAR_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FF0) ||\
|
|
((IT) == CAN_IT_FOV0)|| ((IT) == CAN_IT_FF1) ||\
|
|
((IT) == CAN_IT_FOV1)|| ((IT) == CAN_IT_EWG) ||\
|
|
((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\
|
|
((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\
|
|
((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/* Time out for INAK bit */
|
|
#define INAK_TIMEOUT ((uint32_t)0x0000FFFF)
|
|
/* Time out for SLAK bit */
|
|
#define SLAK_TIMEOUT ((uint32_t)0x0000FFFF)
|
|
|
|
/* Mailboxes definition */
|
|
#define CAN_TXMAILBOX_0 ((uint8_t)0x00)
|
|
#define CAN_TXMAILBOX_1 ((uint8_t)0x01)
|
|
#define CAN_TXMAILBOX_2 ((uint8_t)0x02)
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/* Exported macro ------------------------------------------------------------*/
|
|
|
|
/** @brief Reset CAN handle state
|
|
* @param __HANDLE__: specifies the CAN Handle.
|
|
* @retval None
|
|
*/
|
|
#define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET)
|
|
|
|
/**
|
|
* @brief Enable the specified CAN interrupts.
|
|
* @param __HANDLE__: CAN handle
|
|
* @param __INTERRUPT__: CAN Interrupt
|
|
* @retval None
|
|
*/
|
|
#define __HAL_CAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
|
|
|
|
/**
|
|
* @brief Disable the specified CAN interrupts.
|
|
* @param __HANDLE__: CAN handle
|
|
* @param __INTERRUPT__: CAN Interrupt
|
|
* @retval None
|
|
*/
|
|
#define __HAL_CAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
|
|
|
|
/**
|
|
* @brief Return the number of pending received messages.
|
|
* @param __HANDLE__: CAN handle
|
|
* @param __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
|
|
* @retval The number of pending message.
|
|
*/
|
|
#define __HAL_CAN_MSG_PENDING(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
|
|
((uint8_t)((__HANDLE__)->Instance->RF0R&(uint32_t)0x03)) : ((uint8_t)((__HANDLE__)->Instance->RF1R&(uint32_t)0x03)))
|
|
|
|
/** @brief Check whether the specified CAN flag is set or not.
|
|
* @param __HANDLE__: CAN Handle
|
|
* @param __FLAG__: specifies the flag to check.
|
|
* This parameter can be one of the following values:
|
|
* @arg CAN_TSR_RQCP0: Request MailBox0 Flag
|
|
* @arg CAN_TSR_RQCP1: Request MailBox1 Flag
|
|
* @arg CAN_TSR_RQCP2: Request MailBox2 Flag
|
|
* @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag
|
|
* @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag
|
|
* @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag
|
|
* @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag
|
|
* @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag
|
|
* @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag
|
|
* @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
|
|
* @arg CAN_FLAG_FF0: FIFO 0 Full Flag
|
|
* @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
|
|
* @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
|
|
* @arg CAN_FLAG_FF1: FIFO 1 Full Flag
|
|
* @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
|
|
* @arg CAN_FLAG_WKU: Wake up Flag
|
|
* @arg CAN_FLAG_SLAK: Sleep acknowledge Flag
|
|
* @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag
|
|
* @arg CAN_FLAG_EWG: Error Warning Flag
|
|
* @arg CAN_FLAG_EPV: Error Passive Flag
|
|
* @arg CAN_FLAG_BOF: Bus-Off Flag
|
|
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
|
*/
|
|
#define CAN_FLAG_MASK ((uint32_t)0x000000FF)
|
|
#define __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__) \
|
|
((((__FLAG__) >> 8) == 5)? ((((__HANDLE__)->Instance->TSR) & (1 << ((__FLAG__) & CAN_FLAG_MASK))) == (1 << ((__FLAG__) & CAN_FLAG_MASK))): \
|
|
(((__FLAG__) >> 8) == 2)? ((((__HANDLE__)->Instance->RF0R) & (1 << ((__FLAG__) & CAN_FLAG_MASK))) == (1 << ((__FLAG__) & CAN_FLAG_MASK))): \
|
|
(((__FLAG__) >> 8) == 4)? ((((__HANDLE__)->Instance->RF1R) & (1 << ((__FLAG__) & CAN_FLAG_MASK))) == (1 << ((__FLAG__) & CAN_FLAG_MASK))): \
|
|
(((__FLAG__) >> 8) == 1)? ((((__HANDLE__)->Instance->MSR) & (1 << ((__FLAG__) & CAN_FLAG_MASK))) == (1 << ((__FLAG__) & CAN_FLAG_MASK))): \
|
|
((((__HANDLE__)->Instance->ESR) & (1 << ((__FLAG__) & CAN_FLAG_MASK))) == (1 << ((__FLAG__) & CAN_FLAG_MASK))))
|
|
|
|
/** @brief Clear the specified CAN pending flag.
|
|
* @param __HANDLE__: CAN Handle.
|
|
* @param __FLAG__: specifies the flag to check.
|
|
* This parameter can be one of the following values:
|
|
* @arg CAN_TSR_RQCP0: Request MailBox0 Flag
|
|
* @arg CAN_TSR_RQCP1: Request MailBox1 Flag
|
|
* @arg CAN_TSR_RQCP2: Request MailBox2 Flag
|
|
* @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag
|
|
* @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag
|
|
* @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag
|
|
* @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag
|
|
* @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag
|
|
* @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag
|
|
* @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
|
|
* @arg CAN_FLAG_FF0: FIFO 0 Full Flag
|
|
* @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
|
|
* @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
|
|
* @arg CAN_FLAG_FF1: FIFO 1 Full Flag
|
|
* @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
|
|
* @arg CAN_FLAG_WKU: Wake up Flag
|
|
* @arg CAN_FLAG_SLAK: Sleep acknowledge Flag
|
|
* @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag
|
|
* @arg CAN_FLAG_EWG: Error Warning Flag
|
|
* @arg CAN_FLAG_EPV: Error Passive Flag
|
|
* @arg CAN_FLAG_BOF: Bus-Off Flag
|
|
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
|
*/
|
|
#define __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \
|
|
((((__FLAG__) >> 8) == 5)? (((__HANDLE__)->Instance->TSR) = ~((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK))): \
|
|
(((__FLAG__) >> 8) == 2)? (((__HANDLE__)->Instance->RF0R) = ~((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK))): \
|
|
(((__FLAG__) >> 8) == 4)? (((__HANDLE__)->Instance->RF1R) = ~((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK))): \
|
|
(((__FLAG__) >> 8) == 1)? (((__HANDLE__)->Instance->MSR) = ~((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK))): \
|
|
(((__HANDLE__)->Instance->ESR) = ~((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK))))
|
|
|
|
/** @brief Check if the specified CAN interrupt source is enabled or disabled.
|
|
* @param __HANDLE__: CAN Handle
|
|
* @param __INTERRUPT__: specifies the CAN interrupt source to check.
|
|
* This parameter can be one of the following values:
|
|
* @arg CAN_IT_TME: Transmit mailbox empty interrupt enable
|
|
* @arg CAN_IT_FMP0: FIFO0 message pending interrupt enablev
|
|
* @arg CAN_IT_FMP1: FIFO1 message pending interrupt enable
|
|
* @retval The new state of __IT__ (TRUE or FALSE).
|
|
*/
|
|
#define __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
|
|
|
/**
|
|
* @brief Check the transmission status of a CAN Frame.
|
|
* @param __HANDLE__: CAN Handle
|
|
* @param __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission.
|
|
* @retval The new status of transmission (TRUE or FALSE).
|
|
*/
|
|
#define __HAL_CAN_TRANSMIT_STATUS(__HANDLE__, __TRANSMITMAILBOX__)\
|
|
(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) == (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) :\
|
|
((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) == (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) :\
|
|
((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)) == (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)))
|
|
|
|
|
|
|
|
/**
|
|
* @brief Release the specified receive FIFO.
|
|
* @param __HANDLE__: CAN handle
|
|
* @param __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
|
|
* @retval None
|
|
*/
|
|
#define __HAL_CAN_FIFO_RELEASE(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
|
|
((__HANDLE__)->Instance->RF0R |= CAN_RF0R_RFOM0) : ((__HANDLE__)->Instance->RF1R |= CAN_RF1R_RFOM1))
|
|
|
|
/**
|
|
* @brief Cancel a transmit request.
|
|
* @param __HANDLE__: CAN Handle
|
|
* @param __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission.
|
|
* @retval None
|
|
*/
|
|
#define __HAL_CAN_CANCEL_TRANSMIT(__HANDLE__, __TRANSMITMAILBOX__)\
|
|
(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ0) :\
|
|
((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ1) :\
|
|
((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ2))
|
|
|
|
/**
|
|
* @brief Enable or disable the DBG Freeze for CAN.
|
|
* @param __HANDLE__: CAN Handle
|
|
* @param __NEWSTATE__: new state of the CAN peripheral.
|
|
* This parameter can be: ENABLE (CAN reception/transmission is frozen
|
|
* during debug. Reception FIFOs can still be accessed/controlled normally)
|
|
* or DISABLE (CAN is working during debug).
|
|
* @retval None
|
|
*/
|
|
#define __HAL_CAN_DBG_FREEZE(__HANDLE__, __NEWSTATE__) (((__NEWSTATE__) == ENABLE)? \
|
|
((__HANDLE__)->Instance->MCR |= CAN_MCR_DBF) : ((__HANDLE__)->Instance->MCR &= ~CAN_MCR_DBF))
|
|
|
|
/* Exported functions --------------------------------------------------------*/
|
|
|
|
/* Initialization/de-initialization functions ***********************************/
|
|
HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan);
|
|
HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig);
|
|
HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan);
|
|
void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan);
|
|
void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan);
|
|
|
|
/* I/O operation functions ******************************************************/
|
|
HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef *hcan, uint32_t Timeout);
|
|
HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef *hcan);
|
|
HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef *hcan, uint8_t FIFONumber, uint32_t Timeout);
|
|
HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef *hcan, uint8_t FIFONumber);
|
|
HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef *hcan);
|
|
HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan);
|
|
|
|
/* Peripheral State functions ***************************************************/
|
|
void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan);
|
|
uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan);
|
|
HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan);
|
|
|
|
void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan);
|
|
void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan);
|
|
void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan);
|
|
|
|
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif /* __STM32F4xx_CAN_H */
|
|
|
|
|
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|