376 lines
14 KiB
C
376 lines
14 KiB
C
/*
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* Taken from ST Cube library and modified. See below for original header.
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*
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* Modifications copyright (c) 2021 Blues Wireless Contributors
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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/**
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******************************************************************************
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* @file system_stm32l4xx.c
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* @author MCD Application Team
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* @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File
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*
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* This file provides two functions and one global variable to be called from
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* user application:
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* - SystemInit(): This function is called at startup just after reset and
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* before branch to main program. This call is made inside
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* the "startup_stm32l4xx.s" file.
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*
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* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
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* by the user application to setup the SysTick
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* timer or configure other parameters.
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*
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* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
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* be called whenever the core clock is changed
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* during program execution.
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*
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* After each device reset the MSI (4 MHz) is used as system clock source.
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* Then SystemInit() function is called, in "startup_stm32l4xx.s" file, to
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* configure the system clock before to branch to main program.
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*
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* This file configures the system clock as follows:
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*=============================================================================
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*-----------------------------------------------------------------------------
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* System Clock source | MSI
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*-----------------------------------------------------------------------------
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* SYSCLK(Hz) | 4000000
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*-----------------------------------------------------------------------------
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* HCLK(Hz) | 4000000
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*-----------------------------------------------------------------------------
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* AHB Prescaler | 1
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*-----------------------------------------------------------------------------
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* APB1 Prescaler | 1
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*-----------------------------------------------------------------------------
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* APB2 Prescaler | 1
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*-----------------------------------------------------------------------------
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* PLL_M | 1
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*-----------------------------------------------------------------------------
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* PLL_N | 8
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*-----------------------------------------------------------------------------
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* PLL_P | 7
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*-----------------------------------------------------------------------------
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* PLL_Q | 2
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*-----------------------------------------------------------------------------
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* PLL_R | 2
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*-----------------------------------------------------------------------------
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* PLLSAI1_P | NA
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*-----------------------------------------------------------------------------
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* PLLSAI1_Q | NA
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*-----------------------------------------------------------------------------
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* PLLSAI1_R | NA
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*-----------------------------------------------------------------------------
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* PLLSAI2_P | NA
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*-----------------------------------------------------------------------------
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* PLLSAI2_Q | NA
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*-----------------------------------------------------------------------------
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* PLLSAI2_R | NA
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*-----------------------------------------------------------------------------
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* Require 48MHz for USB OTG FS, | Disabled
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* SDIO and RNG clock |
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*-----------------------------------------------------------------------------
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*=============================================================================
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******************************************************************************
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* @attention
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*
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* <h2><center>© Copyright (c) 2017 STMicroelectronics.
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* All rights reserved.</center></h2>
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*
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* This software component is licensed by ST under Apache License, Version 2.0,
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* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/Apache-2.0
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*
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******************************************************************************
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*/
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/** @addtogroup CMSIS
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* @{
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*/
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/** @addtogroup stm32l4xx_system
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* @{
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*/
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/** @addtogroup STM32L4xx_System_Private_Includes
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* @{
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*/
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#include "stm32l4xx.h"
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#include <math.h>
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/**
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* @}
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*/
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/** @addtogroup STM32L4xx_System_Private_TypesDefinitions
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* @{
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*/
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/**
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* @}
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*/
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/** @addtogroup STM32L4xx_System_Private_Defines
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* @{
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*/
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#if !defined(HSE_VALUE)
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#define HSE_VALUE 8000000U /*!< Value of the External oscillator in Hz */
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#endif /* HSE_VALUE */
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#if !defined(MSI_VALUE)
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#define MSI_VALUE 4000000U /*!< Value of the Internal oscillator in Hz*/
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#endif /* MSI_VALUE */
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#if !defined(HSI_VALUE)
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#define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/
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#endif /* HSI_VALUE */
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/* Note: Following vector table addresses must be defined in line with linker
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configuration. */
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/*!< Uncomment the following line if you need to relocate the vector table
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anywhere in Flash or Sram, else the vector table is kept at the automatic
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remap of boot address selected */
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/* #define USER_VECT_TAB_ADDRESS */
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#if defined(USER_VECT_TAB_ADDRESS)
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/*!< Uncomment the following line if you need to relocate your vector Table
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in Sram else user remap will be done in Flash. */
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/* #define VECT_TAB_SRAM */
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#if defined(VECT_TAB_SRAM)
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#define VECT_TAB_BASE_ADDRESS SRAM1_BASE /*!< Vector Table base address field.
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This value must be a multiple of 0x200. */
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#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
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This value must be a multiple of 0x200. */
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#else
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#define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field.
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This value must be a multiple of 0x200. */
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#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
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This value must be a multiple of 0x200. */
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#endif /* VECT_TAB_SRAM */
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#endif /* USER_VECT_TAB_ADDRESS */
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/******************************************************************************/
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/**
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* @}
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*/
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/** @addtogroup STM32L4xx_System_Private_Macros
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* @{
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*/
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/**
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* @}
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*/
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/** @addtogroup STM32L4xx_System_Private_Variables
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* @{
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*/
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/* The SystemCoreClock variable is updated in three ways:
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1) by calling CMSIS function SystemCoreClockUpdate()
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2) by calling HAL API function HAL_RCC_GetHCLKFreq()
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3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
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Note: If you use this function to configure the system clock; then there
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is no need to call the 2 first functions listed above, since SystemCoreClock
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variable is updated automatically.
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*/
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uint32_t SystemCoreClock = 4000000U;
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const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U};
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const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U};
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const uint32_t MSIRangeTable[12] = {100000U, 200000U, 400000U, 800000U, 1000000U, 2000000U, \
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4000000U, 8000000U, 16000000U, 24000000U, 32000000U, 48000000U};
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/**
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* @}
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*/
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/** @addtogroup STM32L4xx_System_Private_FunctionPrototypes
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* @{
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*/
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/**
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* @}
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*/
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/** @addtogroup STM32L4xx_System_Private_Functions
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* @{
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*/
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/**
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* @brief Setup the microcontroller system.
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* @retval None
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*/
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void SystemInit(void) {
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/* FPU settings ------------------------------------------------------------*/
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#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
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SCB->CPACR |= ((3UL << 20U) | (3UL << 22U)); /* set CP10 and CP11 Full Access */
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#endif
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/* Reset the RCC clock configuration to the default reset state ------------*/
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/* Set MSION bit */
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RCC->CR |= RCC_CR_MSION;
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/* Reset CFGR register */
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RCC->CFGR = 0x00000000U;
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/* Reset HSEON, CSSON , HSION, and PLLON bits */
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RCC->CR &= 0xEAF6FFFFU;
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/* Reset PLLCFGR register */
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RCC->PLLCFGR = 0x00001000U;
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/* Reset HSEBYP bit */
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RCC->CR &= 0xFFFBFFFFU;
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/* Disable all interrupts */
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RCC->CIER = 0x00000000U;
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#if !(BOARD_VTOR_DEFER) // only set VTOR if the bootloader hasn't already
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#if defined(USER_VECT_TAB_ADDRESS)
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/* Configure the Vector Table location -------------------------------------*/
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SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;
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#endif
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#endif
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}
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/**
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* @brief Update SystemCoreClock variable according to Clock Register Values.
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* The SystemCoreClock variable contains the core clock (HCLK), it can
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* be used by the user application to setup the SysTick timer or configure
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* other parameters.
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*
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* @note Each time the core clock (HCLK) changes, this function must be called
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* to update SystemCoreClock variable value. Otherwise, any configuration
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* based on this variable will be incorrect.
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*
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* @note - The system frequency computed by this function is not the real
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* frequency in the chip. It is calculated based on the predefined
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* constant and the selected clock source:
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*
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* - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
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*
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* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
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*
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* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
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*
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* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
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* or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
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*
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* (*) MSI_VALUE is a constant defined in stm32l4xx_hal.h file (default value
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* 4 MHz) but the real value may vary depending on the variations
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* in voltage and temperature.
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*
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* (**) HSI_VALUE is a constant defined in stm32l4xx_hal.h file (default value
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* 16 MHz) but the real value may vary depending on the variations
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* in voltage and temperature.
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*
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* (***) HSE_VALUE is a constant defined in stm32l4xx_hal.h file (default value
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* 8 MHz), user has to ensure that HSE_VALUE is same as the real
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* frequency of the crystal used. Otherwise, this function may
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* have wrong result.
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*
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* - The result of this function could be not correct when using fractional
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* value for HSE crystal.
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*
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* @retval None
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*/
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void SystemCoreClockUpdate(void) {
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uint32_t tmp, msirange, pllvco, pllsource, pllm, pllr;
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/* Get MSI Range frequency--------------------------------------------------*/
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if ((RCC->CR & RCC_CR_MSIRGSEL) == 0U) { /* MSISRANGE from RCC_CSR applies */
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msirange = (RCC->CSR & RCC_CSR_MSISRANGE) >> 8U;
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} else { /* MSIRANGE from RCC_CR applies */
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msirange = (RCC->CR & RCC_CR_MSIRANGE) >> 4U;
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}
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/*MSI frequency range in HZ*/
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msirange = MSIRangeTable[msirange];
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/* Get SYSCLK source -------------------------------------------------------*/
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switch (RCC->CFGR & RCC_CFGR_SWS)
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{
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case 0x00: /* MSI used as system clock source */
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SystemCoreClock = msirange;
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break;
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case 0x04: /* HSI used as system clock source */
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SystemCoreClock = HSI_VALUE;
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break;
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case 0x08: /* HSE used as system clock source */
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SystemCoreClock = HSE_VALUE;
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break;
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case 0x0C: /* PLL used as system clock source */
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/* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
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SYSCLK = PLL_VCO / PLLR
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*/
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pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
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pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4U) + 1U;
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switch (pllsource)
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{
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case 0x02: /* HSI used as PLL clock source */
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pllvco = (HSI_VALUE / pllm);
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break;
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case 0x03: /* HSE used as PLL clock source */
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pllvco = (HSE_VALUE / pllm);
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break;
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default: /* MSI used as PLL clock source */
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pllvco = (msirange / pllm);
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break;
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}
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pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 8U);
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pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25U) + 1U) * 2U;
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SystemCoreClock = pllvco / pllr;
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break;
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default:
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SystemCoreClock = msirange;
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break;
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}
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/* Compute HCLK clock frequency --------------------------------------------*/
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/* Get HCLK prescaler */
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tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)];
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/* HCLK clock frequency */
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SystemCoreClock >>= tmp;
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}
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/**
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* @}
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*/
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/**
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* @}
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*/
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/**
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* @}
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*/
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/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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