5e990cc27f
The RT1176 has two cores, but the actual firmware supports only the CM7. There are currently no good plans on how to use the CM4. The actual MIMXRT1170_EVK board is on par with the existing MIMXRT boards, with the following extensions: - Use 64 MB RAM for the heap. - Support both LAN interfaces as LAN(0) and LAN(1), with LAN(1) being the 1GB interface. The dual LAN port interface can eventually be adapted as well for the RT1062 MCU. This work was done in collaboration with @alphaFred.
139 lines
4.3 KiB
C
139 lines
4.3 KiB
C
/*
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* This file is part of the MicroPython project, http://micropython.org/
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*
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* Based on tinyusb/hw/bsp/teensy_40/teensy40.c
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2018, hathach (tinyusb.org)
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* Copyright (c) 2020, Jim Mussared
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "py/runtime.h"
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#include "tusb.h"
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#include "fsl_device_registers.h"
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#include "fsl_gpio.h"
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#include "fsl_iomuxc.h"
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#include "fsl_clock.h"
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#include "fsl_lpuart.h"
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#include CLOCK_CONFIG_H
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#include "modmachine.h"
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const uint8_t dcd_data[] = { 0x00 };
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void usb_phy0_init(uint8_t d_cal, uint8_t txcal45dp, uint8_t txcal45dn);
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void board_init(void) {
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// Clean and enable cache
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SCB_CleanDCache();
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SCB_EnableDCache();
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SCB_EnableICache();
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// Init clock
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BOARD_BootClockRUN();
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SystemCoreClockUpdate();
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// Enable IOCON clock
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CLOCK_EnableClock(kCLOCK_Iomuxc);
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// SDRAM
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#if MICROPY_HW_SDRAM_AVAIL
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mimxrt_sdram_init();
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#endif
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// 1ms tick timer
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SysTick_Config(SystemCoreClock / 1000);
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// USB0
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usb_phy0_init(0b0111, 0b0110, 0b0110); // Configure nominal values for D_CAL and TXCAL45DP/DN
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// ADC
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machine_adc_init();
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// SDCard
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#if MICROPY_PY_MACHINE_SDCARD
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machine_sdcard_init0();
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#endif
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#if MICROPY_PY_MACHINE_I2S
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machine_i2s_init0();
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#endif
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// RTC
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machine_rtc_start();
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// OCRAM wait states (discarded, but code kept)
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#if 0
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MECC1->PIPE_ECC_EN =
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MECC_PIPE_ECC_EN_READ_DATA_WAIT_EN(1) |
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MECC_PIPE_ECC_EN_READ_ADDR_PIPE_EN(1) |
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MECC_PIPE_ECC_EN_WRITE_DATA_PIPE_EN(1) |
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MECC_PIPE_ECC_EN_WRITE_ADDR_PIPE_EN(1);
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MECC2->PIPE_ECC_EN =
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MECC_PIPE_ECC_EN_READ_DATA_WAIT_EN(1) |
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MECC_PIPE_ECC_EN_READ_ADDR_PIPE_EN(1) |
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MECC_PIPE_ECC_EN_WRITE_DATA_PIPE_EN(1) |
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MECC_PIPE_ECC_EN_WRITE_ADDR_PIPE_EN(1);
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FLEXRAM->FLEXRAM_CTRL =
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FLEXRAM_FLEXRAM_CTRL_OCRAM_RDATA_WAIT_EN(1) |
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FLEXRAM_FLEXRAM_CTRL_OCRAM_RADDR_PIPELINE_EN(1) |
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FLEXRAM_FLEXRAM_CTRL_OCRAM_WRDATA_PIPELINE_EN(1) |
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FLEXRAM_FLEXRAM_CTRL_OCRAM_WRADDR_PIPELINE_EN(1);
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#endif
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}
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void usb_phy0_init(uint8_t d_cal, uint8_t txcal45dp, uint8_t txcal45dn) {
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#ifdef USBPHY1
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USBPHY_Type *usb_phy = USBPHY1;
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#else
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USBPHY_Type *usb_phy = USBPHY;
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#endif
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CLOCK_EnableUsbhs0PhyPllClock(kCLOCK_Usbphy480M, BOARD_XTAL0_CLK_HZ);
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CLOCK_EnableUsbhs0Clock(kCLOCK_Usb480M, BOARD_XTAL0_CLK_HZ);
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#if defined(MIMXRT117x_SERIES)
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usb_phy->TRIM_OVERRIDE_EN = USBPHY_TRIM_OVERRIDE_EN_TRIM_DIV_SEL_OVERRIDE(1) |
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USBPHY_TRIM_OVERRIDE_EN_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE(1) |
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USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_D_CAL_OVERRIDE(1) |
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USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DP_OVERRIDE(1) |
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USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DN_OVERRIDE(1); // Enable override for D_CAL and TXCAL45DP/DN
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#endif
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usb_phy->PWD = 0U; // Set all bits in PWD register to normal operation
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usb_phy->TX = ((usb_phy->TX & (~(USBPHY_TX_D_CAL_MASK | USBPHY_TX_TXCAL45DM_MASK | USBPHY_TX_TXCAL45DP_MASK))) |
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(USBPHY_TX_D_CAL(d_cal) | USBPHY_TX_TXCAL45DP(txcal45dp) | USBPHY_TX_TXCAL45DM(txcal45dn))); // Configure values for D_CAL and TXCAL45DP/DN
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}
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void USB_OTG1_IRQHandler(void) {
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tud_int_handler(0);
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tud_task();
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__SEV();
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}
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void USB_OTG2_IRQHandler(void) {
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tud_int_handler(1);
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tud_task();
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__SEV();
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}
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