This commit improves pllvalues.py to generate PLL values for H7 MCUs that are valid (VCO in and out are in range) and extend for the entire range of SYSCLK values up to 400MHz (up to 480MHz is currently unsupported).
This commit improves pllvalues.py to generate PLL values for H7 MCUs that are valid (VCO in and out are in range) and extend for the entire range of SYSCLK values up to 400MHz (up to 480MHz is currently unsupported).