2e86233263
After the previous commit this macro is no longer needed by the native emitter because live heap pointers are no longer stored in generated native machine code.
339 lines
16 KiB
C
339 lines
16 KiB
C
/*
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* This file is part of the MicroPython project, http://micropython.org/
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2013, 2014 Damien P. George
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#ifndef MICROPY_INCLUDED_PY_ASMTHUMB_H
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#define MICROPY_INCLUDED_PY_ASMTHUMB_H
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#include <assert.h>
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#include "py/misc.h"
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#include "py/asmbase.h"
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#define ASM_THUMB_REG_R0 (0)
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#define ASM_THUMB_REG_R1 (1)
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#define ASM_THUMB_REG_R2 (2)
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#define ASM_THUMB_REG_R3 (3)
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#define ASM_THUMB_REG_R4 (4)
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#define ASM_THUMB_REG_R5 (5)
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#define ASM_THUMB_REG_R6 (6)
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#define ASM_THUMB_REG_R7 (7)
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#define ASM_THUMB_REG_R8 (8)
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#define ASM_THUMB_REG_R9 (9)
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#define ASM_THUMB_REG_R10 (10)
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#define ASM_THUMB_REG_R11 (11)
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#define ASM_THUMB_REG_R12 (12)
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#define ASM_THUMB_REG_R13 (13)
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#define ASM_THUMB_REG_R14 (14)
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#define ASM_THUMB_REG_R15 (15)
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#define ASM_THUMB_REG_LR (REG_R14)
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#define ASM_THUMB_CC_EQ (0x0)
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#define ASM_THUMB_CC_NE (0x1)
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#define ASM_THUMB_CC_CS (0x2)
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#define ASM_THUMB_CC_CC (0x3)
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#define ASM_THUMB_CC_MI (0x4)
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#define ASM_THUMB_CC_PL (0x5)
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#define ASM_THUMB_CC_VS (0x6)
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#define ASM_THUMB_CC_VC (0x7)
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#define ASM_THUMB_CC_HI (0x8)
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#define ASM_THUMB_CC_LS (0x9)
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#define ASM_THUMB_CC_GE (0xa)
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#define ASM_THUMB_CC_LT (0xb)
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#define ASM_THUMB_CC_GT (0xc)
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#define ASM_THUMB_CC_LE (0xd)
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typedef struct _asm_thumb_t {
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mp_asm_base_t base;
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uint32_t push_reglist;
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uint32_t stack_adjust;
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} asm_thumb_t;
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void asm_thumb_end_pass(asm_thumb_t *as);
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void asm_thumb_entry(asm_thumb_t *as, int num_locals);
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void asm_thumb_exit(asm_thumb_t *as);
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// argument order follows ARM, in general dest is first
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// note there is a difference between movw and mov.w, and many others!
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#define ASM_THUMB_OP_IT (0xbf00)
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#define ASM_THUMB_OP_ITE_EQ (0xbf0c)
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#define ASM_THUMB_OP_ITE_CS (0xbf2c)
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#define ASM_THUMB_OP_ITE_MI (0xbf4c)
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#define ASM_THUMB_OP_ITE_VS (0xbf6c)
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#define ASM_THUMB_OP_ITE_HI (0xbf8c)
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#define ASM_THUMB_OP_ITE_GE (0xbfac)
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#define ASM_THUMB_OP_ITE_GT (0xbfcc)
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#define ASM_THUMB_OP_NOP (0xbf00)
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#define ASM_THUMB_OP_WFI (0xbf30)
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#define ASM_THUMB_OP_CPSID_I (0xb672) // cpsid i, disable irq
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#define ASM_THUMB_OP_CPSIE_I (0xb662) // cpsie i, enable irq
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void asm_thumb_op16(asm_thumb_t *as, uint op);
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void asm_thumb_op32(asm_thumb_t *as, uint op1, uint op2);
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static inline void asm_thumb_it_cc(asm_thumb_t *as, uint cc, uint mask)
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{ asm_thumb_op16(as, ASM_THUMB_OP_IT | (cc << 4) | mask); }
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// FORMAT 1: move shifted register
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#define ASM_THUMB_FORMAT_1_LSL (0x0000)
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#define ASM_THUMB_FORMAT_1_LSR (0x0800)
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#define ASM_THUMB_FORMAT_1_ASR (0x1000)
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#define ASM_THUMB_FORMAT_1_ENCODE(op, rlo_dest, rlo_src, offset) \
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((op) | ((offset) << 6) | ((rlo_src) << 3) | (rlo_dest))
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static inline void asm_thumb_format_1(asm_thumb_t *as, uint op, uint rlo_dest, uint rlo_src, uint offset) {
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assert(rlo_dest < ASM_THUMB_REG_R8);
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assert(rlo_src < ASM_THUMB_REG_R8);
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asm_thumb_op16(as, ASM_THUMB_FORMAT_1_ENCODE(op, rlo_dest, rlo_src, offset));
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}
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// FORMAT 2: add/subtract
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#define ASM_THUMB_FORMAT_2_ADD (0x1800)
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#define ASM_THUMB_FORMAT_2_SUB (0x1a00)
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#define ASM_THUMB_FORMAT_2_REG_OPERAND (0x0000)
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#define ASM_THUMB_FORMAT_2_IMM_OPERAND (0x0400)
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#define ASM_THUMB_FORMAT_2_ENCODE(op, rlo_dest, rlo_src, src_b) \
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((op) | ((src_b) << 6) | ((rlo_src) << 3) | (rlo_dest))
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static inline void asm_thumb_format_2(asm_thumb_t *as, uint op, uint rlo_dest, uint rlo_src, int src_b) {
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assert(rlo_dest < ASM_THUMB_REG_R8);
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assert(rlo_src < ASM_THUMB_REG_R8);
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asm_thumb_op16(as, ASM_THUMB_FORMAT_2_ENCODE(op, rlo_dest, rlo_src, src_b));
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}
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static inline void asm_thumb_add_rlo_rlo_rlo(asm_thumb_t *as, uint rlo_dest, uint rlo_src_a, uint rlo_src_b)
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{ asm_thumb_format_2(as, ASM_THUMB_FORMAT_2_ADD | ASM_THUMB_FORMAT_2_REG_OPERAND, rlo_dest, rlo_src_a, rlo_src_b); }
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static inline void asm_thumb_add_rlo_rlo_i3(asm_thumb_t *as, uint rlo_dest, uint rlo_src_a, int i3_src)
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{ asm_thumb_format_2(as, ASM_THUMB_FORMAT_2_ADD | ASM_THUMB_FORMAT_2_IMM_OPERAND, rlo_dest, rlo_src_a, i3_src); }
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static inline void asm_thumb_sub_rlo_rlo_rlo(asm_thumb_t *as, uint rlo_dest, uint rlo_src_a, uint rlo_src_b)
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{ asm_thumb_format_2(as, ASM_THUMB_FORMAT_2_SUB | ASM_THUMB_FORMAT_2_REG_OPERAND, rlo_dest, rlo_src_a, rlo_src_b); }
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static inline void asm_thumb_sub_rlo_rlo_i3(asm_thumb_t *as, uint rlo_dest, uint rlo_src_a, int i3_src)
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{ asm_thumb_format_2(as, ASM_THUMB_FORMAT_2_SUB | ASM_THUMB_FORMAT_2_IMM_OPERAND, rlo_dest, rlo_src_a, i3_src); }
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// FORMAT 3: move/compare/add/subtract immediate
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// These instructions all do zero extension of the i8 value
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#define ASM_THUMB_FORMAT_3_MOV (0x2000)
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#define ASM_THUMB_FORMAT_3_CMP (0x2800)
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#define ASM_THUMB_FORMAT_3_ADD (0x3000)
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#define ASM_THUMB_FORMAT_3_SUB (0x3800)
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#define ASM_THUMB_FORMAT_3_ENCODE(op, rlo, i8) ((op) | ((rlo) << 8) | (i8))
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static inline void asm_thumb_format_3(asm_thumb_t *as, uint op, uint rlo, int i8) {
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assert(rlo < ASM_THUMB_REG_R8);
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asm_thumb_op16(as, ASM_THUMB_FORMAT_3_ENCODE(op, rlo, i8));
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}
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static inline void asm_thumb_mov_rlo_i8(asm_thumb_t *as, uint rlo, int i8) { asm_thumb_format_3(as, ASM_THUMB_FORMAT_3_MOV, rlo, i8); }
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static inline void asm_thumb_cmp_rlo_i8(asm_thumb_t *as, uint rlo, int i8) { asm_thumb_format_3(as, ASM_THUMB_FORMAT_3_CMP, rlo, i8); }
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static inline void asm_thumb_add_rlo_i8(asm_thumb_t *as, uint rlo, int i8) { asm_thumb_format_3(as, ASM_THUMB_FORMAT_3_ADD, rlo, i8); }
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static inline void asm_thumb_sub_rlo_i8(asm_thumb_t *as, uint rlo, int i8) { asm_thumb_format_3(as, ASM_THUMB_FORMAT_3_SUB, rlo, i8); }
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// FORMAT 4: ALU operations
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#define ASM_THUMB_FORMAT_4_AND (0x4000)
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#define ASM_THUMB_FORMAT_4_EOR (0x4040)
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#define ASM_THUMB_FORMAT_4_LSL (0x4080)
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#define ASM_THUMB_FORMAT_4_LSR (0x40c0)
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#define ASM_THUMB_FORMAT_4_ASR (0x4100)
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#define ASM_THUMB_FORMAT_4_ADC (0x4140)
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#define ASM_THUMB_FORMAT_4_SBC (0x4180)
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#define ASM_THUMB_FORMAT_4_ROR (0x41c0)
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#define ASM_THUMB_FORMAT_4_TST (0x4200)
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#define ASM_THUMB_FORMAT_4_NEG (0x4240)
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#define ASM_THUMB_FORMAT_4_CMP (0x4280)
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#define ASM_THUMB_FORMAT_4_CMN (0x42c0)
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#define ASM_THUMB_FORMAT_4_ORR (0x4300)
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#define ASM_THUMB_FORMAT_4_MUL (0x4340)
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#define ASM_THUMB_FORMAT_4_BIC (0x4380)
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#define ASM_THUMB_FORMAT_4_MVN (0x43c0)
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void asm_thumb_format_4(asm_thumb_t *as, uint op, uint rlo_dest, uint rlo_src);
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static inline void asm_thumb_cmp_rlo_rlo(asm_thumb_t *as, uint rlo_dest, uint rlo_src) { asm_thumb_format_4(as, ASM_THUMB_FORMAT_4_CMP, rlo_dest, rlo_src); }
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// FORMAT 5: hi register operations (add, cmp, mov, bx)
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// For add/cmp/mov, at least one of the args must be a high register
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#define ASM_THUMB_FORMAT_5_ADD (0x4400)
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#define ASM_THUMB_FORMAT_5_BX (0x4700)
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#define ASM_THUMB_FORMAT_5_ENCODE(op, r_dest, r_src) \
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((op) | ((r_dest) << 4 & 0x0080) | ((r_src) << 3) | ((r_dest) & 0x0007))
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static inline void asm_thumb_format_5(asm_thumb_t *as, uint op, uint r_dest, uint r_src) {
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asm_thumb_op16(as, ASM_THUMB_FORMAT_5_ENCODE(op, r_dest, r_src));
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}
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static inline void asm_thumb_add_reg_reg(asm_thumb_t *as, uint r_dest, uint r_src) {
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asm_thumb_format_5(as, ASM_THUMB_FORMAT_5_ADD, r_dest, r_src);
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}
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static inline void asm_thumb_bx_reg(asm_thumb_t *as, uint r_src) {
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asm_thumb_format_5(as, ASM_THUMB_FORMAT_5_BX, 0, r_src);
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}
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// FORMAT 9: load/store with immediate offset
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// For word transfers the offset must be aligned, and >>2
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// FORMAT 10: load/store halfword
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// The offset must be aligned, and >>1
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// The load is zero extended into the register
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#define ASM_THUMB_FORMAT_9_STR (0x6000)
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#define ASM_THUMB_FORMAT_9_LDR (0x6800)
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#define ASM_THUMB_FORMAT_9_WORD_TRANSFER (0x0000)
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#define ASM_THUMB_FORMAT_9_BYTE_TRANSFER (0x1000)
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#define ASM_THUMB_FORMAT_10_STRH (0x8000)
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#define ASM_THUMB_FORMAT_10_LDRH (0x8800)
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#define ASM_THUMB_FORMAT_9_10_ENCODE(op, rlo_dest, rlo_base, offset) \
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((op) | (((offset) << 6) & 0x07c0) | ((rlo_base) << 3) | (rlo_dest))
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static inline void asm_thumb_format_9_10(asm_thumb_t *as, uint op, uint rlo_dest, uint rlo_base, uint offset)
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{ asm_thumb_op16(as, ASM_THUMB_FORMAT_9_10_ENCODE(op, rlo_dest, rlo_base, offset)); }
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static inline void asm_thumb_str_rlo_rlo_i5(asm_thumb_t *as, uint rlo_src, uint rlo_base, uint word_offset)
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{ asm_thumb_format_9_10(as, ASM_THUMB_FORMAT_9_STR | ASM_THUMB_FORMAT_9_WORD_TRANSFER, rlo_src, rlo_base, word_offset); }
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static inline void asm_thumb_strb_rlo_rlo_i5(asm_thumb_t *as, uint rlo_src, uint rlo_base, uint byte_offset)
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{ asm_thumb_format_9_10(as, ASM_THUMB_FORMAT_9_STR | ASM_THUMB_FORMAT_9_BYTE_TRANSFER, rlo_src, rlo_base, byte_offset); }
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static inline void asm_thumb_strh_rlo_rlo_i5(asm_thumb_t *as, uint rlo_src, uint rlo_base, uint byte_offset)
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{ asm_thumb_format_9_10(as, ASM_THUMB_FORMAT_10_STRH, rlo_src, rlo_base, byte_offset); }
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static inline void asm_thumb_ldr_rlo_rlo_i5(asm_thumb_t *as, uint rlo_dest, uint rlo_base, uint word_offset)
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{ asm_thumb_format_9_10(as, ASM_THUMB_FORMAT_9_LDR | ASM_THUMB_FORMAT_9_WORD_TRANSFER, rlo_dest, rlo_base, word_offset); }
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static inline void asm_thumb_ldrb_rlo_rlo_i5(asm_thumb_t *as, uint rlo_dest, uint rlo_base, uint byte_offset)
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{ asm_thumb_format_9_10(as, ASM_THUMB_FORMAT_9_LDR | ASM_THUMB_FORMAT_9_BYTE_TRANSFER , rlo_dest, rlo_base, byte_offset); }
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static inline void asm_thumb_ldrh_rlo_rlo_i5(asm_thumb_t *as, uint rlo_dest, uint rlo_base, uint byte_offset)
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{ asm_thumb_format_9_10(as, ASM_THUMB_FORMAT_10_LDRH, rlo_dest, rlo_base, byte_offset); }
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// TODO convert these to above format style
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#define ASM_THUMB_OP_MOVW (0xf240)
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#define ASM_THUMB_OP_MOVT (0xf2c0)
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void asm_thumb_mov_reg_reg(asm_thumb_t *as, uint reg_dest, uint reg_src);
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void asm_thumb_mov_reg_i16(asm_thumb_t *as, uint mov_op, uint reg_dest, int i16_src);
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// these return true if the destination is in range, false otherwise
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bool asm_thumb_b_n_label(asm_thumb_t *as, uint label);
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bool asm_thumb_bcc_nw_label(asm_thumb_t *as, int cond, uint label, bool wide);
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bool asm_thumb_bl_label(asm_thumb_t *as, uint label);
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void asm_thumb_mov_reg_i32(asm_thumb_t *as, uint reg_dest, mp_uint_t i32_src); // convenience
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void asm_thumb_mov_reg_i32_optimised(asm_thumb_t *as, uint reg_dest, int i32_src); // convenience
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void asm_thumb_mov_local_reg(asm_thumb_t *as, int local_num_dest, uint rlo_src); // convenience
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void asm_thumb_mov_reg_local(asm_thumb_t *as, uint rlo_dest, int local_num); // convenience
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void asm_thumb_mov_reg_local_addr(asm_thumb_t *as, uint rlo_dest, int local_num); // convenience
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void asm_thumb_mov_reg_pcrel(asm_thumb_t *as, uint rlo_dest, uint label);
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void asm_thumb_b_label(asm_thumb_t *as, uint label); // convenience: picks narrow or wide branch
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void asm_thumb_bcc_label(asm_thumb_t *as, int cc, uint label); // convenience: picks narrow or wide branch
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void asm_thumb_bl_ind(asm_thumb_t *as, void *fun_ptr, uint fun_id, uint reg_temp); // convenience
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#if GENERIC_ASM_API
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// The following macros provide a (mostly) arch-independent API to
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// generate native code, and are used by the native emitter.
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#define ASM_WORD_SIZE (4)
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#define REG_RET ASM_THUMB_REG_R0
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#define REG_ARG_1 ASM_THUMB_REG_R0
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#define REG_ARG_2 ASM_THUMB_REG_R1
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#define REG_ARG_3 ASM_THUMB_REG_R2
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#define REG_ARG_4 ASM_THUMB_REG_R3
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// rest of args go on stack
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#define REG_TEMP0 ASM_THUMB_REG_R0
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#define REG_TEMP1 ASM_THUMB_REG_R1
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#define REG_TEMP2 ASM_THUMB_REG_R2
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#define REG_LOCAL_1 ASM_THUMB_REG_R4
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#define REG_LOCAL_2 ASM_THUMB_REG_R5
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#define REG_LOCAL_3 ASM_THUMB_REG_R6
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#define REG_LOCAL_NUM (3)
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#define ASM_T asm_thumb_t
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#define ASM_END_PASS asm_thumb_end_pass
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#define ASM_ENTRY asm_thumb_entry
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#define ASM_EXIT asm_thumb_exit
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#define ASM_JUMP asm_thumb_b_label
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#define ASM_JUMP_IF_REG_ZERO(as, reg, label, bool_test) \
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do { \
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asm_thumb_cmp_rlo_i8(as, reg, 0); \
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asm_thumb_bcc_label(as, ASM_THUMB_CC_EQ, label); \
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} while (0)
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#define ASM_JUMP_IF_REG_NONZERO(as, reg, label, bool_test) \
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do { \
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asm_thumb_cmp_rlo_i8(as, reg, 0); \
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asm_thumb_bcc_label(as, ASM_THUMB_CC_NE, label); \
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} while (0)
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#define ASM_JUMP_IF_REG_EQ(as, reg1, reg2, label) \
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do { \
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asm_thumb_cmp_rlo_rlo(as, reg1, reg2); \
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asm_thumb_bcc_label(as, ASM_THUMB_CC_EQ, label); \
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} while (0)
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#define ASM_JUMP_REG(as, reg) asm_thumb_bx_reg((as), (reg))
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#define ASM_CALL_IND(as, ptr, idx) asm_thumb_bl_ind(as, ptr, idx, ASM_THUMB_REG_R3)
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#define ASM_MOV_LOCAL_REG(as, local_num, reg) asm_thumb_mov_local_reg((as), (local_num), (reg))
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#define ASM_MOV_REG_IMM(as, reg_dest, imm) asm_thumb_mov_reg_i32_optimised((as), (reg_dest), (imm))
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#define ASM_MOV_REG_LOCAL(as, reg_dest, local_num) asm_thumb_mov_reg_local((as), (reg_dest), (local_num))
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#define ASM_MOV_REG_REG(as, reg_dest, reg_src) asm_thumb_mov_reg_reg((as), (reg_dest), (reg_src))
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#define ASM_MOV_REG_LOCAL_ADDR(as, reg_dest, local_num) asm_thumb_mov_reg_local_addr((as), (reg_dest), (local_num))
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#define ASM_MOV_REG_PCREL(as, rlo_dest, label) asm_thumb_mov_reg_pcrel((as), (rlo_dest), (label))
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#define ASM_LSL_REG_REG(as, reg_dest, reg_shift) asm_thumb_format_4((as), ASM_THUMB_FORMAT_4_LSL, (reg_dest), (reg_shift))
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#define ASM_ASR_REG_REG(as, reg_dest, reg_shift) asm_thumb_format_4((as), ASM_THUMB_FORMAT_4_ASR, (reg_dest), (reg_shift))
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#define ASM_OR_REG_REG(as, reg_dest, reg_src) asm_thumb_format_4((as), ASM_THUMB_FORMAT_4_ORR, (reg_dest), (reg_src))
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#define ASM_XOR_REG_REG(as, reg_dest, reg_src) asm_thumb_format_4((as), ASM_THUMB_FORMAT_4_EOR, (reg_dest), (reg_src))
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#define ASM_AND_REG_REG(as, reg_dest, reg_src) asm_thumb_format_4((as), ASM_THUMB_FORMAT_4_AND, (reg_dest), (reg_src))
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#define ASM_ADD_REG_REG(as, reg_dest, reg_src) asm_thumb_add_rlo_rlo_rlo((as), (reg_dest), (reg_dest), (reg_src))
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#define ASM_SUB_REG_REG(as, reg_dest, reg_src) asm_thumb_sub_rlo_rlo_rlo((as), (reg_dest), (reg_dest), (reg_src))
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#define ASM_MUL_REG_REG(as, reg_dest, reg_src) asm_thumb_format_4((as), ASM_THUMB_FORMAT_4_MUL, (reg_dest), (reg_src))
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#define ASM_LOAD_REG_REG(as, reg_dest, reg_base) asm_thumb_ldr_rlo_rlo_i5((as), (reg_dest), (reg_base), 0)
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#define ASM_LOAD_REG_REG_OFFSET(as, reg_dest, reg_base, word_offset) asm_thumb_ldr_rlo_rlo_i5((as), (reg_dest), (reg_base), (word_offset))
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#define ASM_LOAD8_REG_REG(as, reg_dest, reg_base) asm_thumb_ldrb_rlo_rlo_i5((as), (reg_dest), (reg_base), 0)
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#define ASM_LOAD16_REG_REG(as, reg_dest, reg_base) asm_thumb_ldrh_rlo_rlo_i5((as), (reg_dest), (reg_base), 0)
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#define ASM_LOAD32_REG_REG(as, reg_dest, reg_base) asm_thumb_ldr_rlo_rlo_i5((as), (reg_dest), (reg_base), 0)
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#define ASM_STORE_REG_REG(as, reg_src, reg_base) asm_thumb_str_rlo_rlo_i5((as), (reg_src), (reg_base), 0)
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#define ASM_STORE_REG_REG_OFFSET(as, reg_src, reg_base, word_offset) asm_thumb_str_rlo_rlo_i5((as), (reg_src), (reg_base), (word_offset))
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#define ASM_STORE8_REG_REG(as, reg_src, reg_base) asm_thumb_strb_rlo_rlo_i5((as), (reg_src), (reg_base), 0)
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#define ASM_STORE16_REG_REG(as, reg_src, reg_base) asm_thumb_strh_rlo_rlo_i5((as), (reg_src), (reg_base), 0)
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#define ASM_STORE32_REG_REG(as, reg_src, reg_base) asm_thumb_str_rlo_rlo_i5((as), (reg_src), (reg_base), 0)
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#endif // GENERIC_ASM_API
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#endif // MICROPY_INCLUDED_PY_ASMTHUMB_H
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