8785645a95
The port currently implements support for GPIO, RTC, ExtInt and the WiFi subsystem. A small file system is available in the serial flash. A bootloader which makes OTA updates possible, is also part of this initial implementation.
745 lines
21 KiB
C
745 lines
21 KiB
C
//*****************************************************************************
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//
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// sdhost.c
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//
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// Driver for the SD Host (SDHost) Interface
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//
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// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
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//
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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//*****************************************************************************
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//*****************************************************************************
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//
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//! \addtogroup Secure_Digital_Host_api
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//! @{
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//
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//*****************************************************************************
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#include "inc/hw_types.h"
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#include "inc/hw_memmap.h"
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#include "inc/hw_mmchs.h"
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#include "inc/hw_ints.h"
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#include "inc/hw_apps_config.h"
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#include "interrupt.h"
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#include "sdhost.h"
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//*****************************************************************************
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//
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//! Configures SDHost module.
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//!
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//! \param ulBase is the base address of SDHost module.
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//!
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//! This function configures the SDHost module, enabling internal sub-modules.
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//!
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//! \return None.
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//
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//*****************************************************************************
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void
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SDHostInit(unsigned long ulBase)
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{
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//
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// Assert module reset
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//
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HWREG(ulBase + MMCHS_O_SYSCONFIG) = 0x2;
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//
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// Wait for soft reset to complete
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//
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while( !(HWREG(ulBase + MMCHS_O_SYSCONFIG) & 0x1) )
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{
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}
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//
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// Assert internal reset
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//
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HWREG(ulBase + MMCHS_O_SYSCTL) |= (1 << 24);
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//
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// Wait for Reset to complete
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//
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while( (HWREG(ulBase + MMCHS_O_SYSCTL) & (0x1 << 24)) )
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{
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}
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//
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// Set capability register, 1.8 and 3.0 V
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//
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HWREG(ulBase + MMCHS_O_CAPA) = (0x7 <<24);
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//
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// Select bus voltage, 3.0 V
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//
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HWREG(ulBase + MMCHS_O_HCTL) |= 0x7 << 9;
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//
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// Power up the bus
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//
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HWREG(ulBase + MMCHS_O_HCTL) |= 1 << 8;
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//
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// Wait for power on
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//
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while( !(HWREG(ulBase + MMCHS_O_HCTL) & (1<<8)) )
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{
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}
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HWREG(ulBase + MMCHS_O_CON) |= 1 << 21;
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//
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// Un-mask all events
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//
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HWREG(ulBase + MMCHS_O_IE) = 0xFFFFFFFF;
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}
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//*****************************************************************************
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//
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//! Resets SDHost command line
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//!
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//! \param ulBase is the base address of SDHost module.
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//!
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//! This function assers a soft reset for the command line
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//!
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//! \return None.
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//
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//*****************************************************************************
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void
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SDHostCmdReset(unsigned long ulBase)
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{
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HWREG(ulBase + MMCHS_O_SYSCTL) |= 1 << 25;
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while( (HWREG(ulBase + MMCHS_O_SYSCTL) & (1 << 25)) )
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{
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}
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}
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//*****************************************************************************
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//
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//! Sends command over SDHost interface
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//!
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//! \param ulBase is the base address of SDHost module.
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//! \param ulCmd is the command to send.
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//! \param ulArg is the argument for the command.
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//!
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//! This function send command to the attached card over the SDHost interface.
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//!
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//! The \e ulCmd parameter can be one of \b SDHOST_CMD_0 to \b SDHOST_CMD_63.
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//! It can be logically ORed with one or more of the following:
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//! - \b SDHOST_MULTI_BLK for multi-block transfer
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//! - \b SDHOST_WR_CMD if command is followed by write data
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//! - \b SDHOST_RD_CMD if command is followed by read data
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//! - \b SDHOST_DMA_EN if SDHost need to generate DMA request.
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//! - \b SDHOST_RESP_LEN_136 if 136 bit response is expected
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//! - \b SDHOST_RESP_LEN_48 if 48 bit response is expected
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//! - \b SDHOST_RESP_LEN_48B if 48 bit response with busy bit is expected
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//!
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//! The parameter \e ulArg is the argument for the command
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//!
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//! \return Returns 0 on success, -1 otherwise.
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//
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//*****************************************************************************
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long
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SDHostCmdSend(unsigned long ulBase, unsigned long ulCmd, unsigned ulArg)
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{
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//
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// Set Data Timeout
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//
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HWREG(ulBase + MMCHS_O_SYSCTL) |= 0x000E0000;
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//
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// Check for cmd inhabit
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//
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if( (HWREG(ulBase + MMCHS_O_PSTATE) & 0x1))
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{
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return -1;
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}
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//
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// Set the argument
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//
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HWREG(ulBase + MMCHS_O_ARG) = ulArg;
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//
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// Send the command
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//
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HWREG(ulBase + MMCHS_O_CMD) = ulCmd;
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return 0;
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}
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//*****************************************************************************
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//
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//! Writes a data word into the SDHost write buffer.
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//!
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//! \param ulBase is the base address of SDHost module.
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//! \param ulData is data word to be transfered.
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//!
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//! This function writes a single data word into the SDHost write buffer. The
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//! function returns \b true if there was a space available in the buffer else
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//! returns \b false.
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//!
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//! \return Return \b true on success, \b false otherwise.
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//
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//*****************************************************************************
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tBoolean
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SDHostDataNonBlockingWrite(unsigned long ulBase, unsigned long ulData)
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{
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//
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// See if there is a space in the write buffer
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//
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if( (HWREG(ulBase + MMCHS_O_PSTATE) & (1<<10)) )
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{
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//
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// Write the data into the buffer
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//
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HWREG(ulBase + MMCHS_O_DATA) = ulData;
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//
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// Success.
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//
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return(true);
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}
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else
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{
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//
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// No free sapce, failure.
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//
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return(false);
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}
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}
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//*****************************************************************************
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//
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//! Waits to write a data word into the SDHost write buffer.
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//!
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//! \param ulBase is the base address of SDHost module.
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//! \param ulData is data word to be transfered.
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//!
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//! This function writes \e ulData into the SDHost write buffer. If there is no
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//! space in the write buffer this function waits until there is a space
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//! available before returning.
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//!
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//! \return None.
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//
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//*****************************************************************************
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void
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SDHostDataWrite(unsigned long ulBase, unsigned long ulData)
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{
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//
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// Wait until space is available
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//
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while( !(HWREG(ulBase + MMCHS_O_PSTATE) & (1<<10)) )
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{
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}
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//
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// Write the data
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//
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HWREG(ulBase + MMCHS_O_DATA) = ulData;
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}
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//*****************************************************************************
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//
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//! Waits for a data word from the SDHost read buffer
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//!
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//! \param ulBase is the base address of SDHost module.
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//! \param pulData is pointer to read data variable.
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//!
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//! This function reads a single data word from the SDHost read buffer. If there
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//! is no data available in the buffer the function will wait until a data
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//! word is received before returning.
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//!
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//! \return None.
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//
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//*****************************************************************************
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void
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SDHostDataRead(unsigned long ulBase, unsigned long *pulData)
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{
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//
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// Wait until data is available
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//
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while( !(HWREG(ulBase + MMCHS_O_PSTATE) & (1<<11)) )
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{
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}
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//
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// Read the data
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//
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*pulData = HWREG(ulBase + MMCHS_O_DATA);
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}
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//*****************************************************************************
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//
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//! Reads single data word from the SDHost read buffer
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//!
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//! \param ulBase is the base address of SDHost module.
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//! \param pulData is pointer to read data variable.
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//!
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//! This function reads a data word from the SDHost read buffer. The
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//! function returns \b true if there was data available in to buffer else
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//! returns \b false.
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//!
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//! \return Return \b true on success, \b false otherwise.
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//
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//*****************************************************************************
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tBoolean
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SDHostDataNonBlockingRead(unsigned long ulBase, unsigned long *pulData)
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{
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//
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// See if there is any data in the read buffer.
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//
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if( (HWREG(ulBase + MMCHS_O_PSTATE) & (1<11)) )
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{
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//
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// Read the data word.
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//
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*pulData = HWREG(ulBase + MMCHS_O_DATA);
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//
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// Success
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//
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return(true);
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}
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else
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{
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//
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// No data available, failure.
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//
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return(false);
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}
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}
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//*****************************************************************************
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//
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//! Registers the interrupt handler for SDHost interrupt
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//!
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//! \param ulBase is the base address of SDHost module
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//! \param pfnHandler is a pointer to the function to be called when the
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//! SDHost interrupt occurs.
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//!
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//! This function does the actual registering of the interrupt handler. This
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//! function enables the global interrupt in the interrupt controller; specific
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//! SDHost interrupts must be enabled via SDHostIntEnable(). It is the
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//! interrupt handler's responsibility to clear the interrupt source.
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//!
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//! \sa IntRegister() for important information about registering interrupt
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//! handlers.
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//!
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//! \return None.
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//
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//*****************************************************************************
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void
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SDHostIntRegister(unsigned long ulBase, void (*pfnHandler)(void))
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{
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//
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// Register the interrupt handler.
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//
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IntRegister(INT_MMCHS, pfnHandler);
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//
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// Enable the SDHost interrupt.
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//
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IntEnable(INT_MMCHS);
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}
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//*****************************************************************************
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//
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//! Unregisters the interrupt handler for SDHost interrupt
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//!
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//! \param ulBase is the base address of SDHost module
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//!
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//! This function does the actual unregistering of the interrupt handler. It
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//! clears the handler to be called when a SDHost interrupt occurs. This
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//! function also masks off the interrupt in the interrupt controller so that
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//! the interrupt handler no longer is called.
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//!
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//! \sa IntRegister() for important information about registering interrupt
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//! handlers.
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//!
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//! \return None.
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//
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//*****************************************************************************
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void
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SDHostIntUnregister(unsigned long ulBase)
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{
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//
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// Disable the SDHost interrupt.
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//
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IntDisable(INT_MMCHS);
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//
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// Unregister the interrupt handler.
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//
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IntUnregister(INT_MMCHS);
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}
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//*****************************************************************************
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//
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//! Enable individual interrupt source for the specified SDHost
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//!
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//! \param ulBase is the base address of SDHost module.
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//! \param ulIntFlags is a bit mask of the interrupt sources to be enabled.
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//!
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//! This function enables the indicated SDHost interrupt sources. Only the
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//! sources that are enabled can be reflected to the processor interrupt;
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//! disabled sources have no effect on the processor.
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//!
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//! The \e ulIntFlags parameter is the logical OR of any of the following:
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//! - \b SDHOST_INT_CC Command Complete interrupt
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//! - \b SDHOST_INT_TC Transfer Complete interrupt
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//! - \b SDHOST_INT_BWR Buffer Write Ready interrupt
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//! - \b SDHOST_INT_BRR Buffer Read Ready interrupt
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//! - \b SDHOST_INT_ERRI Error interrupt
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//! - \b SDHOST_INT_CTO Command Timeout error interrupt
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//! - \b SDHOST_INT_CEB Command End Bit error interrupt
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//! - \b SDHOST_INT_DTO Data Timeout error interrupt
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//! - \b SDHOST_INT_DCRC Data CRC error interrupt
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//! - \b SDHOST_INT_DEB Data End Bit error
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//! - \b SDHOST_INT_CERR Cart Status Error interrupt
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//! - \b SDHOST_INT_BADA Bad Data error interrupt
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//! - \b SDHOST_INT_DMARD Read DMA done interrupt
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//! - \b SDHOST_INT_DMAWR Write DMA done interrupt
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//!
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//! Note that SDHOST_INT_ERRI can only be used with \sa SDHostIntStatus()
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//! and is internally logical OR of all error status bits. Setting this bit
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//! alone as \e ulIntFlags doesn't generates any interrupt.
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//!
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//! \return None.
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//
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//*****************************************************************************
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void
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SDHostIntEnable(unsigned long ulBase,unsigned long ulIntFlags)
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{
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//
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// Enable DMA done interrupts
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//
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HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_MASK_CLR) =
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(ulIntFlags >> 30);
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//
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// Enable the individual interrupt sources
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//
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HWREG(ulBase + MMCHS_O_ISE) |= (ulIntFlags & 0x3FFFFFFF);
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}
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//*****************************************************************************
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//
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//! Enable individual interrupt source for the specified SDHost
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//!
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//! \param ulBase is the base address of SDHost module.
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//! \param ulIntFlags is a bit mask of the interrupt sources to be enabled.
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//!
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//! This function disables the indicated SDHost interrupt sources. Only the
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//! sources that are enabled can be reflected to the processor interrupt;
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//! disabled sources have no effect on the processor.
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//!
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//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags
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//! parameter to SDHostIntEnable().
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//!
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//! \return None.
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//
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//*****************************************************************************
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void
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SDHostIntDisable(unsigned long ulBase,unsigned long ulIntFlags)
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{
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//
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// Disable DMA done interrupts
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//
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HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_MASK_SET) =
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(ulIntFlags >> 30);
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//
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// Disable the individual interrupt sources
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//
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HWREG(ulBase + MMCHS_O_ISE) &= ~(ulIntFlags & 0x3FFFFFFF);
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}
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//*****************************************************************************
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//
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//! Gets the current interrupt status.
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//!
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//! \param ulBase is the base address of SDHost module.
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//!
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//! This function returns the interrupt status for the specified SDHost.
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//!
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//! \return Returns the current interrupt status, enumerated as a bit field of
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//! values described in SDHostIntEnable().
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//
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//*****************************************************************************
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unsigned long
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SDHostIntStatus(unsigned long ulBase)
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{
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unsigned long ulIntStatus;
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//
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// Get DMA done interrupt status
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//
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ulIntStatus = HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_MASK_SET);
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ulIntStatus = (ulIntStatus << 30);
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//
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// Return the status of individual interrupt sources
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//
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ulIntStatus |= (HWREG(ulBase + MMCHS_O_STAT) & 0x3FFFFFFF);
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return(ulIntStatus);
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}
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//*****************************************************************************
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//
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//! Clears the individual interrupt sources.
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//!
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//! \param ulBase is the base address of SDHost module.
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//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared.
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//!
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//! The specified SDHost interrupt sources are cleared, so that they no longer
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//! assert. This function must be called in the interrupt handler to keep the
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//! interrupt from being recognized again immediately upon exit.
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//!
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//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags
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//! parameter to SDHostIntEnable().
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//!
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//! \return None.
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//
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//*****************************************************************************
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void
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SDHostIntClear(unsigned long ulBase,unsigned long ulIntFlags)
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{
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//
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// Clear DMA done interrupts
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//
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HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_ACK) =
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(ulIntFlags >> 30);
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//
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// Clear the individual interrupt sources
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//
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HWREG(ulBase + MMCHS_O_STAT) = (ulIntFlags & 0x3FFFFFFF);
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}
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//*****************************************************************************
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//
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//! Sets the card status error mask.
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//!
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//! \param ulBase is the base address of SDHost module
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//! \param ulErrMask is the bit mask of card status errors to be enabled
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//!
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//! This function sets the card status error mask for response type R1, R1b,
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//! R5, R5b and R6 response. The parameter \ulErrMask is the bit mask of card
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//! status errors to be enabled, if the corresponding bits in the 'card status'
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//! field of a respose are set then the host controller indicates a card error
|
|
//! interrupt status. Only bits referenced as type E (error) in status field in
|
|
//! the response can set a card status error.
|
|
//!
|
|
//! \return None
|
|
//
|
|
//*****************************************************************************
|
|
void
|
|
SDHostCardErrorMaskSet(unsigned long ulBase, unsigned long ulErrMask)
|
|
{
|
|
//
|
|
// Set the card status error mask
|
|
//
|
|
HWREG(ulBase + MMCHS_O_CSRE) = ulErrMask;
|
|
}
|
|
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Gets the card status error mask.
|
|
//!
|
|
//! \param ulBase is the base address of SDHost module
|
|
//!
|
|
//! This function gets the card status error mask for response type R1, R1b,
|
|
//! R5, R5b and R6 response.
|
|
//!
|
|
//! \return Returns the current card status error.
|
|
//
|
|
//*****************************************************************************
|
|
unsigned long
|
|
SDHostCardErrorMaskGet(unsigned long ulBase)
|
|
{
|
|
//
|
|
// Return the card status error mask
|
|
//
|
|
return(HWREG(ulBase + MMCHS_O_CSRE));
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Sets the SD Card clock.
|
|
//!
|
|
//! \param ulBase is the base address of SDHost module
|
|
//! \param ulSDHostClk is the rate of clock supplied to SDHost module
|
|
//! \param ulCardClk is the required SD interface clock
|
|
//!
|
|
//! This function configures the SDHost interface to supply the specified clock
|
|
//! to the connected card.
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
void
|
|
SDHostSetExpClk(unsigned long ulBase, unsigned long ulSDHostClk,
|
|
unsigned long ulCardClk)
|
|
{
|
|
unsigned long ulDiv;
|
|
|
|
//
|
|
// Disable card clock
|
|
//
|
|
HWREG(ulBase + MMCHS_O_SYSCTL) &= ~0x4;
|
|
|
|
//
|
|
// Enable internal clock
|
|
//
|
|
HWREG(ulBase + MMCHS_O_SYSCTL) |= 0x1;
|
|
|
|
ulDiv = ((ulSDHostClk/ulCardClk) & 0x3FF);
|
|
|
|
//
|
|
// Set clock divider,
|
|
//
|
|
HWREG(ulBase + MMCHS_O_SYSCTL) = ((HWREG(ulBase + MMCHS_O_SYSCTL) &
|
|
~0x0000FFC0)| (ulDiv) << 6);
|
|
|
|
//
|
|
// Wait for clock to stablize
|
|
//
|
|
while( !(HWREG(ulBase + MMCHS_O_SYSCTL) & 0x2) )
|
|
{
|
|
|
|
}
|
|
|
|
//
|
|
// Enable card clock
|
|
//
|
|
HWREG(ulBase + MMCHS_O_SYSCTL) |= 0x4;
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Get the response for the last command.
|
|
//!
|
|
//! \param ulBase is the base address of SDHost module
|
|
//! \param ulRespnse is 128-bit response.
|
|
//!
|
|
//! This function gets the response from the SD card for the last command
|
|
//! send.
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
void
|
|
SDHostRespGet(unsigned long ulBase, unsigned long ulRespnse[4])
|
|
{
|
|
|
|
//
|
|
// Read the responses.
|
|
//
|
|
ulRespnse[0] = HWREG(ulBase + MMCHS_O_RSP10);
|
|
ulRespnse[1] = HWREG(ulBase + MMCHS_O_RSP32);
|
|
ulRespnse[2] = HWREG(ulBase + MMCHS_O_RSP54);
|
|
ulRespnse[3] = HWREG(ulBase + MMCHS_O_RSP76);
|
|
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Set the block size for data transfer
|
|
//!
|
|
//! \param ulBase is the base address of SDHost module
|
|
//! \param ulBlkSize is the transfer block size in bytes
|
|
//!
|
|
//! This function sets the block size the data transfer.
|
|
//!
|
|
//! The parameter \e ulBlkSize is size of each data block in bytes.
|
|
//! This should be in range 0 - 2^10.
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
void
|
|
SDHostBlockSizeSet(unsigned long ulBase, unsigned short ulBlkSize)
|
|
{
|
|
//
|
|
// Set the block size
|
|
//
|
|
HWREG(ulBase + MMCHS_O_BLK) = ((HWREG(ulBase + MMCHS_O_BLK) & 0x00000FFF)|
|
|
(ulBlkSize & 0xFFF));
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Set the block size and count for data transfer
|
|
//!
|
|
//! \param ulBase is the base address of SDHost module
|
|
//! \param ulBlkCount is the number of blocks
|
|
//!
|
|
//! This function sets block count for the data transfer. This needs to be set
|
|
//! for each block transfer. \sa SDHostBlockSizeSet()
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
void
|
|
SDHostBlockCountSet(unsigned long ulBase, unsigned short ulBlkCount)
|
|
{
|
|
unsigned long ulRegVal;
|
|
|
|
//
|
|
// Read the current value
|
|
//
|
|
ulRegVal = HWREG(ulBase + MMCHS_O_BLK);
|
|
|
|
//
|
|
// Set the number of blocks
|
|
//
|
|
HWREG(ulBase + MMCHS_O_BLK) |= ((ulRegVal & 0x0000FFFF)|
|
|
(ulBlkCount << 16));
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// Close the Doxygen group.
|
|
//! @}
|
|
//
|
|
//*****************************************************************************
|